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CHAPTER 17 INTERRUPT FUNCTIONS
User
’
s Manual U13655EJ2V1UD
261
17.4.5 Pending interrupt requests
There are some instructions that, even if an interrupt request is issued for them while another instruction is being
executed, cause a request acknowledgement to be held pending until the end of execution of the next instruction.
These instructions (instructions for which instruction requests are held pending) are listed below.
MOV
MOV
MOV
MOV1 PSW.bit, CY
MOV1 CY, PSW. bit
AND1
CY, PSW. bit
OR1
CY, PSW. bit
XOR1
CY, PSW. bit
SET1
PSW. bit
CLR1
PSW. bit
RETB
RETI
PUSH PSW
POP
PSW
BT
PSW. bit, $addr16
BF
PSW. bit, $addr16
BTCLR PSW. bit, $addr16
IE
DI
Manipulation instructions for IF0L, IF0H, IF1L, IF1H, MK0L, MK0H, MK1L, MK1H, PR0L, PR0H, PR1L, PR1H,
EGP, and EGN registers.
PSW, #byte
A, PSW
PSW, A
Caution
The BRK instruction is not one of the above-listed instructions. However, a software interrupt
activated by executing the BRK instruction causes the IE flag to be cleared to 0. Therefore,
even if a maskable interrupt request is generated during execution of the BRK instruction, the
interrupt request is not acknowledged. However, non-maskable interrupts are acknowledged.
The timing at which interrupt requests are held pending is shown in Figure 17-14.
Figure 17-14. Pending Interrupt Requests
Remarks 1.
Instruction N: Instruction for which interrupt request is held pending
2.
Instruction M: Instruction other than instruction for which interrupt request is held pending
3.
××
IF
×
(interrupt request) operation is not affected by the value of
××
PR
×
(priority level).
Instruction N
Instruction M
Save PSW and PC, and
jump to interrupt service
Interrupt servicing
program
CPU processing
××
IF
×