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User
’
s Manual U13655EJ2V1UD
7
Major Revisions in This Edition (2/3)
Page
Description
p. 138
Addition of
Figure 7-11. Configuration Diagram for PPG Output
p. 138
Addition of
Figure 7-12. PPG Output Operation Timing
p. 140
Modification of
Figure 7-15. Timing of Pulse-Width Measurement Operation with Free-Running Counter
and One Capture Register (with Both Edges Specified)
p. 142
Modification of
Figure 7-17. CR01 Capture Operation with Rising Edge Specified
p. 142
Modification of
Figure 7-18. Timing of Two-Pulse-Width Measurement Operation with Free-Running
Counter (with Both Edges Specified)
p. 144
Modification of
Figure 7-20. Timing of Pulse-Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
p. 145
Modification of
Figure 7-22. Timing of Pulse-Width Measurement Operation by Means of Restart (with
Rising Edge Specified)
p. 150
p. 150
p. 151
p. 151
p. 152
7.6 Operating Cautions for 16-Bit Timer/Event Counter 0
Modification of
Figure 7-30. Capture Register Data Retention Timing
Modification of
Figure 7-31. Operation Timing of OVF0 Flag
Addition of <2> to <4> to
(9) Capture operation
Modification of <1> in
(10) Compare operation
Addition of <2> to
(11) Edge detection
p. 157
Addition of
Caution 2
to
8.5.1 Interval timer operation
pp. 158, 159
Modification of
Figure 8-4. Timing of Interval Timer Operation (When Using Internal Clock)
p. 160
Addition of
Caution 2
to
8.5.2 External event counter operation
p. 161
Modification of
Figure 8-7. Timing of External Event Counter Operation
p. 162
Modification of
Figure 8-8. Start Timing of 16-Bit Timer Counter 2 (TM2)
pp. 171, 172
Modification of
Figure 9-6. Timing of Interval Timer Operation
p. 173
Modification of
Figure 9-7. Start Timing of 8-Bit Timer Counter 8n (TM8n)
p. 175
Modification of
Figure 10-1. Block Diagram of Watchdog Timer
p. 181
p. 181
Modification of the following contents in
11.3 Sampling Output Timer/Detector Configuration
Modification of
Note
Addition of
Caution
p. 186
p. 187
11.4 Sampling Output Timer/Detector Control Registers
Addition of
Cautions 15
and
16
to
Figure 11-4. Format of SMTD Control Register 0 (TSM0)
Addition of
Caution
to
(8) SMDT sampling level setting register 0 (SMS0)
p. 190
Modification of
Figure 12-1. Block Diagram of MR Sampling
p. 191
Addition of
Caution
to
(2) MRTD compare register 0 (CRM0)
in
12.3 MR Sampling Configuration
p. 192
Addition of
Note
to
Figure 12-2. Format of MRTD Control Register 0 (TCM0)
p. 194
Modification of
Figure 12-4. Format of MR Sampling Control Register 0 (MRM0)
p. 196
Modification of
12.6 Phase Detector Operation
p. 199
Modification of
Figure 13-1. Block Diagram of Clock Output Controller