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CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
365
Figure 7-2. Block Diagram of Each Channel (Example: Channel 4 of 78K0R/IE3)
PRS
013
PRS
003
PRS
012
PRS
011
PRS
010
PRS
023
PRS
022
PRS
021
PRS
020
PRS
033
PRS
032
PRS
031
PRS
030
PRS
002
PRS
001
PRS
000
4
fCLK
TAU0EN
4
TI03
TI05
TO03
TO05
INTTM03
INTTM05
PM12
CKS14 CCS04
CKS04
MAS
TER04
STS042 STS041 STS040
MD042
CIS041 CIS040 MD043
MD041 MD040
CSF
OVF
CK00
CK01
CK03
CK02
CK01
CK00
fMCK
fTCLK
fSUB/4
TIS04
TNFEN04
TT
05
TT
11
TT
10
TT
09
TT
08
TT
07
TT
06
TT
04
TT
03
TT
02
TT
01
TT
00
TS
05
TS
11
TS
10
TS
09
TS
08
TS
07
TS
06
TS
04
TS
03
TS
02
TS
01
TS
00
TE
05
TE
11
TE
10
TE
09
TE
08
TE
07
TE
06
TE
04
TE
03
TE
02
TE
01
TE
00
TOE
05
TOE
11
TOE
10
TOE
09
TOE
08
TOE
07
TOE
06
TOE
04
TOE
03
TOE
02
TOE
01
TOE
00
TOM
05
TOM
11
TOM
10
TOM
09
TOM
08
TOM
07
TOM
06
TOM
04
TOM
03
TOM
02
TOM
01
TOM
00
TOL
05
TOL
11
TOL
10
TOL
09
TOL
08
TOL
07
TOL
06
TOL
04
TOL
03
TOL
02
TOL
01
TOL
00
TOT
05
TOT
11
TOT
10
TOT
09
TOT
08
TOT
07
TOT
06
TOT
04
TOT
03
TOT
02
TOT
01
TOT
00
TDE
05
TDE
11
TDE
10
TDE
09
TDE
08
TDE
07
TDE
06
TDE
04
TDE
03
TDE
02
TDE
01
TDE
00
TO
05
TO
11
TO
10
TO
09
TO
08
TO
07
TO
06
TO
04
TO
03
TO
02
TO
01
TO
00
0
00
TNFEN
SL
TNFEN
11
TNFEN
10
TNFEN
09
TNFEN
07
TNFEN
06
TNFEN
05
TNFEN
04
TNFEN
03
TNFEN
02
0
TIS
07
TIS
06
TIS
05
TIS
04
TIS
03
TIS
02
TIS
01
TIS
00
Timer clock select register 0 (TPS0)
fCLK/20 to
fCLK/215
Selector
fCLK/20 to
fCLK/215
Selector
Peripheral enable register 2
(PER2)
Prescaler
fCLK/20 to
fCLK/215
Selector
fCLK/20 to
fCLK/215
Selector
Prescaler
To channels
8, 9, 10, 11
Timer real-time output
enable register 0 (TRE0)
Timer real-time output
register 0 (TRO0)
Timer real-time control
register 0 (TRC0)
Timer modulation output
enable register 0 (TME0)
Timer output
register 0 (TO0)
Timer output enable
register 0 (TOE0)
Timer channel enable
status register 0 (TE0)
Timer channel stop
register 0 (TT0)
Timer input select
register 0 (TIS0)
Timer channel start
register 0 (TS0)
Timer output level
register 0 (TOL0)
Timer triangle wave
output mode
register 0 (TOT0)
Timer dead time
output enable
register 0 (TDE0)
Timer output mode
register 0 (TOM0)
Noise filter enable
register 2 (NFEN2)
Noise filter enable
register 1 (NFEN1)
Channel 3
TO04
(timer output pin)
INTTM04
(timer interrupt)
Slave/master
controller
Interrupt
controller
Real-time
output selector
Shifting up or down to slave channel
Interrupt signal to
a lower channel
Trigger signal to
a lower channel
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Mode
selection
Edge
detection
Timer
controller
Interrupt
controller
Up/down counter
controller
TI04
(timer
input pin)
Timer mode register 04 (TMR04)
Timer status
register 04 (TSR04)
Output
controller
Overflow
Channel 4
Timer data register 04 (TDR04)
Timer counter register 04 (TCR04)
Slave/master
controller
Output latch
(P12)
Real-time output
selector
Channel 4 period
detection signal
Operation
clock
selection
Count
clock
selection
Trigger
selection
Noise
elimination
enabled/disabled
Selector
Channel 5
Interrupt signal to a higher channel
TRC04
TRE
05
TRE
11
TRE
10
TRE
09
TRE
08
TRE
07
TRE
06
TRE
04
TRE
03
TRE
02
TRE
01
TRE
00
TRO
05
TRO
11
TRO
10
TRO
09
TRO
08
TRO
07
TRO
06
TRO
04
TRO
03
TRO
02
TRO
01
TRO
00
TRC
05
TRC
11
TRC
10
TRC
09
TRC
08
TRC
07
TRC
06
TRC
04
TRC
03
TRC
02
TRC
01
TRC
00
TME
05
TME
11
TME
10
TME
09
TME
08
TME
07
TME
06
TME
04
TME
03
TME
02
TME
01
TME
00
TNFEN
00
TNFEN
08
Remark
The block diagram in Figure 7-2 includes the registers and pins that are to be used in common with timer
array unit TAUS. For details of timer array unit TAUS, refer to CHAPTER 6 TIMER ARRAY UNIT
TAUS.