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CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
420
Figure 7-38. Operation Procedure When Triangular Wave PWM Output Function with Dead Time Is Used (1/2)
Software Operation
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAUS
default
setting
Sets the TPS0 register.
Determines the clock frequencies of CK00 and CK01.
Sets the TMRn, TMRp, and TMRq registers of four
channels to be used (determines operation mode of
channels).
An interval (period) value is set to the TDRn register of
the master channel, a duty factor is set to the TDRp
register of slave channels 2, 6, and a dead time width is
set to the TDRq register of slave channels 3, 7.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TO00, TOp, and TOq pins go into Hi-Z output states.
Sets slave channels.
The TOMp and TOMq bits of the TOM0 register, and
the TOTp and TOTq bits of the TOT0 register are set
to 1 (triangular wave PWM generation).
Sets the TOLp and TOLq bits, and determines the
active levels of the TOp and TOq outputs.
Sets the TDEp and TDEq bits to 1 (dead time control
enable).
Sets the TOn, TOp, and TOq bits, and determines
default levels of TOn, TOp, and TOq.
The TOn, TOp, and TOq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
Channel
default
setting
Sets the TOEn, TOEp, and TOEq bits to 1 and enables
operation of TOn, TOp, and TOq.
Clears the port register and port mode register to 0.
TOn, TOp, and TOq do not change because channels stop
operating.
The TOn, TOp, and TOq pins output the TOn, TOp, and TOq
set levels.
Operation
start
Sets the TOEm (master), and TOEp and TOEq (slaves)
bits to 1 (only when operation is resumed).
The TSn (master), and TSp and TSq (slaves) bits of the
TS0 register are set to 1 at the same time.
The TSn, TSp, and TSq bits automatically return to 0
because they are trigger bits.
TEn = 1, TEp = 1, TEq = 1
When the master channel and slave channels 2, 6 start
counting, and when the MDn0 bit of the TMRn register is
set to 1, INTTMn is generated. Slave channels 3, 7 wait
until slave channels 2, 6 detect INTTMp.
During
operation
The set value of the TDRn (master) register must be
changed during an up status period of slave channels 2,
6.
The set values of the TDRp and TDRq (slaves) register
can be changed.
The TCRn, TCRp, and TCRq registers can always be
read.
The TSRp (slave) register can always be read.
At the master channel, a period is generated and count
operation of slave channels are controlled. A PWM duty is
generated at slave channels 2, 6, and dead time is
generated at slave channels 3, 7.
Triangular wave PWM waveforms with dead times are output
from the TOp and TOq pins by a combined operation of
slave channels 2, 6 and slave channels 3, 7.
Remark
n = 00, 04 p = 02, 06 q = 03, 07
Operation
is
re
su
med.
(from
next
page)