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CHAPTER 12 A/D CONVERTER
User’s Manual U19678EJ1V1UD
590
12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter
<1>
Set bit 5 (ADCEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the A/D
converter.
<2>
Set the A/D conversion time by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of ADM, and set the operation
mode by using bit 6 (ADMD) of ADM.
<3>
Set bit 0 (ADCE) of A/D converter mode register (ADM) to 1 to start the operation of the A/D voltage
comparator.
<4>
Set the channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and
set to input mode by using port mode registers (PM2, PM8, and PM15).
<5>
Set the programmable gain amplifier operation to set the programmable gain amplifier output signal from
PGAI pin (PGAO) for the analog input channel (refer to 8.4.1 Starting comparator and programmable gain
amplifier operation).
<6>
Select one channel for A/D conversion using the analog input channel specification register (ADS).
<7>
Use the A/D converter mode register 1 (ADM1) to set the trigger mode.
<8>
Start the conversion operation by setting bit 7 (ADCS) of ADM to 1.
A timer trigger wait state is entered if the timer trigger mode is set in step <7>.
(<9> to <15> are operations performed by hardware.)
<9>
The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<10> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has ended.
<11> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF by the tap selector.
<12> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF, the MSB is reset to 0.
<13> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
Bit 9 = 1: (3/4) AVREF
Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of SAR is manipulated as follows.
Sampled voltage ≥ Voltage tap: Bit 8 = 1
Sampled voltage < Voltage tap: Bit 8 = 0
<14> Comparison is continued in this way up to bit 0 of SAR.
<15> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<16> Repeat steps <9> to <15>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <8>. To start A/D conversion again when
ADCE = 0, set ADCE to 1, wait for 1
μs or longer, and start <8>. To change a channel of A/D conversion,
start from <6>.
Caution
Make sure the period of <3> to <8> is 1
μs or more.