24
User’s Manual U12697EJ4V1UD
17-5
3-Wire Serial I/O Mode Timing ..........................................................................................................
291
18-1
Serial Bus Configuration Example in I2C Bus Mode .........................................................................
293
18-2
Block Diagram of Clocked Serial Interface (I2C Bus Mode) ..............................................................
294
18-3
Format of I2C Bus Control Register 0 (IICC0) ...................................................................................
296
18-4
Format of I2C Bus Status Register 0 (IICS0) ....................................................................................
301
18-5
Format of Prescaler Mode Register 0 for Serial Clock (SPRM0) ......................................................
304
18-6
Pin Configuration ..............................................................................................................................
307
18-7
Serial Data Transfer Timing of I2C Bus .............................................................................................
308
18-8
Start Condition ..................................................................................................................................
308
18-9
Address .............................................................................................................................................
309
18-10
Transfer Direction Specification ........................................................................................................
309
18-11
Acknowledge Signal ..........................................................................................................................
310
18-12
Stop Condition ..................................................................................................................................
311
18-13
Wait Signal ........................................................................................................................................
312
18-14
Example of Arbitration Timing ...........................................................................................................
335
18-15
Timing of Communication Reservation .............................................................................................
338
18-16
Communication Reservation Acceptance Timing .............................................................................
338
18-17
Communication Reservation Procedure ...........................................................................................
339
18-18
Master Operation Procedure .............................................................................................................
341
18-19
Slave Operating Procedure ..............................................................................................................
342
18-20
Master
→ Slave Communication Example (When Master and Slave Select 9-Clock Wait) .............
344
18-21
Slave
→ Master Communication Example (When Master and Slave Select 9-Clock Wait) .............
347
19-1
Remote Control Output Application Example ...................................................................................
350
19-2
Block Diagram of Clock Output Function ..........................................................................................
351
19-3
Format of Clock Output Control Register (CKS) ...............................................................................
352
19-4
Format of Port 2 Mode Register (PM2) .............................................................................................
353
20-1
Block Diagram of Buzzer Output Function ........................................................................................
354
20-2
Format of Clock Output Control Register (CKS) ...............................................................................
355
20-3
Format of Port 2 Mode Register (PM2) .............................................................................................
356
21-1
Format of External Interrupt Rising Edge Enable Register 0 (EGP0) and External Interrupt
Falling Edge Enable Register 0 (EGN0) ...........................................................................................
357
21-2
Block Diagram of P00 to P05 Pins ....................................................................................................
358
22-1
Interrupt Control Register (xxICn) .....................................................................................................
367
22-2
Format of Interrupt Mask Registers (MK0, MK1) ..............................................................................
371
22-3
Format of In-Service Priority Register (ISPR) ...................................................................................
372
22-4
Format of Interrupt Mode Control Register (IMC) .............................................................................
373
22-5
Format of Watchdog Timer Mode Register (WDM) ...........................................................................
374
22-6
Format of Interrupt Selection Control Register (SNMI) .....................................................................
375
LIST OF FIGURES (5/8)
Figure No.
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