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26
User’s Manual U12697EJ4V1UD
23-1
Format of Memory Expansion Mode Register (MM) .........................................................................
438
23-2
Format of Programmable Wait Control Register 1 (PWC1) ..............................................................
439
23-3
PD784224 Memory Map ................................................................................................................. 441
23-4
PD784225 Memory Map ................................................................................................................. 443
23-5
Instruction Fetch from External Memory in External Memory Expansion Mode ...............................
446
23-6
Read Timing for External Memory in External Memory Expansion Mode .........................................
447
23-7
External Write Timing for External Memory in External Memory Expansion Mode ...........................
448
23-8
Read Modify Write Timing for External Memory in External Memory Expansion Mode ....................
449
23-9
Read/Write Timing by Address Wait Function ...................................................................................
450
23-10
Read Timing by Access Wait Function ..............................................................................................
454
23-11
Write Timing by Access Wait Function ..............................................................................................
456
23-12
Timing by External Wait Signal .........................................................................................................
458
23-13
Configuration of External Access Status Output Function ................................................................
459
23-14
Format of External Access Status Enable Register (EXAE) .............................................................
460
23-15
Example of Local Bus Interface (Multiplexed Bus) ...........................................................................
462
24-1
Standby Function State Transition ....................................................................................................
464
24-2
Format of Standby Control Register (STBC) ....................................................................................
466
24-3
Format of Clock Status Register (PCS) ............................................................................................
467
24-4
Format of Oscillation Stabilization Time Specification Register (OSTS) ...........................................
469
24-5
Operations After Releasing HALT Mode ...........................................................................................
474
24-6
Operations After Releasing STOP Mode ..........................................................................................
483
24-7
Releasing STOP Mode by NMI Input ................................................................................................
486
24-8
Example of Releasing STOP Mode by INTP0 to INTP5 Input ..........................................................
487
24-9
Operations After Releasing IDLE Mode ............................................................................................
491
24-10
Example of Handling Address/Data Bus ...........................................................................................
496
24-11
Flow for Setting Subsystem Clock Operation ...................................................................................
497
24-12
Setting Timing for Subsystem Clock Operation ................................................................................
498
24-13
Flow to Restore Main System Clock Operation ................................................................................
499
24-14
Timing for Restoring Main System Clock Operation .........................................................................
499
25-1
Oscillation of Main System Clock in Reset Period ............................................................................
504
25-2
Receiving Reset Signal .....................................................................................................................
505
26-1
ROM Correction Block Diagram ........................................................................................................
508
26-2
Memory Mapping Example (
PD784225) ......................................................................................... 509
26-3
Format of ROM Correction Address Register (CORAH, CORAL) ....................................................
509
26-4
Format of ROM Correction Control Register (CORC) .......................................................................
510
27-1
Format of Internal Memory Size Switching Register (IMS) ...............................................................
514
27-2
Format of Communication Mode Selection .......................................................................................
517
27-3
Connection of Flashpro III in 3-Wire Serial I/O Mode (When Using 3-Wire Serial I/O 0) ..................
518
27-4
Connection of Flashpro III in 3-Wire Serial I/O Mode (When Using Handshake) .............................
518
27-5
Connection of Flashpro III in UART Mode (When Using UART1) .....................................................
519
LIST OF FIGURES (7/8)
Figure No.
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