參數(shù)資料
型號: UPD78F9221MC-5A4-A
廠商: Renesas Electronics America
文件頁數(shù): 2/125頁
文件大?。?/td> 0K
描述: MCU 8BIT 2KB FLASH 20PIN
標準包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
連通性: LIN,UART/USART
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-LSSOP(0.240",6.10mm 寬)
包裝: 托盤
User’s Manual U16898EJ6V0UD
8
CONTENTS
CHAPTER 1 OVERVIEW.........................................................................................................................14
1.1
Features ......................................................................................................................................14
1.2
Ordering Information .................................................................................................................16
1.3
Pin Configuration (Top View)....................................................................................................17
1.4
78K0S/Kx1+ Product Lineup .....................................................................................................18
1.5
Block Diagram ............................................................................................................................19
1.6
Functional Outline......................................................................................................................20
CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21
2.1
Pin Function List ........................................................................................................................21
2.2
Pin Functions..............................................................................................................................23
2.2.1
P20 to P23 (Port 2)......................................................................................................................23
2.2.2
P30, P31, and P34 (Port 3)..........................................................................................................23
2.2.3
P40 to P45 (Port 4)......................................................................................................................24
2.2.4
P121 to P123 (Port 12) ................................................................................................................24
2.2.5
P130 (Port 13) .............................................................................................................................24
2.2.6
RESET ........................................................................................................................................24
2.2.7
X1 and X2....................................................................................................................................25
2.2.8
AVREF...........................................................................................................................................25
2.2.9
VDD...............................................................................................................................................25
2.2.10
VSS...............................................................................................................................................25
2.3
Pin I/O Circuits and Connection of Unused Pins....................................................................25
CHAPTER 3 CPU ARCHITECTURE ......................................................................................................27
3.1
Memory Space ............................................................................................................................27
3.1.1
Internal program memory space..................................................................................................30
3.1.2
Internal data memory space ........................................................................................................31
3.1.3
Special function register (SFR) area............................................................................................31
3.1.4
Data memory addressing.............................................................................................................31
3.2
Processor Registers ..................................................................................................................34
3.2.1
Control registers ..........................................................................................................................34
3.2.2
General-purpose registers ...........................................................................................................36
3.2.3
Special function registers (SFRs) ................................................................................................37
3.3
Instruction Address Addressing ..............................................................................................43
3.3.1
Relative addressing .....................................................................................................................43
3.3.2
Immediate addressing .................................................................................................................44
3.3.3
Table indirect addressing.............................................................................................................44
3.3.4
Register addressing.....................................................................................................................45
3.4
Operand Address Addressing ..................................................................................................46
3.4.1
Direct addressing.........................................................................................................................46
3.4.2
Short direct addressing................................................................................................................47
3.4.3
Special function register (SFR) addressing .................................................................................48
3.4.4
Register addressing.....................................................................................................................49
3.4.5
Register indirect addressing ........................................................................................................50
3.4.6
Based addressing........................................................................................................................51
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