參數(shù)資料
型號： UPSD3253BV-40T1T
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 101/176頁
文件大?。?/td> 1214K
代理商： UPSD3253BV-40T1T
101/176
μPSD325X DEVICES
Table 81. Transceiver DC Characteristics
Note: 1. V
DD
=5V ± 10%; V
SS
=0V; T
A
=0 to 70
2. Level guaranteed for range of V
DD
= 4.5V to 5.5V
3. With RPU, external idle resistor, 7.5
κ
±2%, D- to V
DD
.
4. C
L
of 50pF(75ns) to 350pF (300ns).
5. Measured at crossover point of differential data signals.
6. USB specification indicates 330ns
Table 82. Transceiver AC Characteristics
Note: 1. V
DD
=5V ± 10%; V
SS
=0V; T
A
=0 to 70
Symb
Parameter
Test Conditions
Min
Max
Unit
V
OH
Static Output High
15k
±5%
2.8
3.6
V
V
OL
Static Output Low
Notes 2,3
—
0.3
V
V
DI
Differential Input Sensitivity
|(D+) - (D-)|, Fig 6.9
0.2
—
V
V
CM
Differential Input Common Mode
Fig 6.9
0.8
2.5
V
V
SE
Single Ended Receiver Threshold
—
0.8
2.0
V
C
IN
Transceiver Capacitance
—
—
20
pF
I
IO
Data Line (D+, D-) Leakage
0V<(D+,D-)<3. 3,
–10
10
μA
R
PU
External Bus Pull-up Resistance, D-
7.5k
±2%
7.35
7.65
k
R
PD
External Bus Pull-down Resistance
15k
±5%
14.25
15.75
k
Parameter
Symb
Min
Max
Unit
Test Conditions
Low Speed Data Rate
fDRATE
1.4775
1.5225
Mbit/s
Ave. bit rate
Receiver Data Jitter Tolerance
tDJR1
–75
75
ns
to next transition,
Differential Input Sensitivity
tDJR2
–45
45
ns
for paired transition,
Differential to EOP Transition Skew
tDEOP
–40
100
ns
Fig 6.10
4
EOP Width at Receiver
tEOPR1
165
—
ns
rejects as EOP
4, 5
EOP Width at Receiver
tEOPR2
675
—
ns
accepts as EOP
4
Source EOP Width
tEOPT
–1.25
1.50
μs
—
Differential Driver Jitter
tUDJ1
–95
95
ns
to next transition,
Differential Driver Jitter
tUDJ2
–150
150
ns
to paired transition,
USB Data Transition Rise Time
tR
75
300
ns
Notes
1, 2, 3
USB Data Transition Fall Time
tF
75
300
ns
Notes
1, 2, 3
Rise/Fall Time Matching
tRFM
80
120
%
t
R
/ t
F
Output Signal Crossover Volt age
VCRS
1.3
2.0
V
—
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