參數(shù)資料
型號： UPSD3253BV-40T1T
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和256Kbit的SRAM
文件頁數(shù)： 81/176頁
文件大?。?/td> 1214K
代理商： UPSD3253BV-40T1T
81/176
μPSD325X DEVICES
Programmer’s Guide for I
2
C and DDC2
The I
2
C serial I/O and DDC Interface operates in
four modes.
I
Master transmitter
I
Master receiver
I
Slave transmitter
I
Slave receiver
Master transmitter mode flow.
1. Read SxSTA.
2. If BBUSY == 1 then
go to step1.
Else then
write slave address to SxDAT and set both
ENI and STA, reset AA in SxCON.
3. Wait for interrupt.
4. Read SxSTA.
If BLOST == 1 or /ACK_REP == 1* then
write dummy data to SxDAT.
Go to step1.
Else then
clear STA.
5. Perform required service routines.
If this datum == LAST then
set STO in SxCON and write last data to Sx-
DAT**.
Go to step 6.
Else then
write next data to SxDAT**.
Go to step3.
6. Wait for interrupt.
Write dummy data to SxDAT**.
Note: 1. (*)
If the master don’t receive the acknowledge from the
slave, it generates the STOP condition and returns to the
IDLE state.
2. (**) This action should be the last in service routine.
Slave transmitter mode flow.
1. Write slave address to SxADR, set AA and ENI
in SxCON.
2. Wait for interrupt.
3. Read SxSTA and write the first data to SxDAT*.
Reset AA in SxCON.
4. Wait for interrupt.
5. Read SxSTA.
If /ACK_REP == 1** then
Go to step7.
Else then
write the next SxDAT*.
Go to step5.
6. Write dummy data to SxDAT*.
Note: 1. (*) These actions should be the last.
2. (**) If the master want to stop the current data requests, it
don’t have to acknowledge to the slave transmitter.
3. If the slave does not receive the acknowledge from the
master, it releases the SDA and enters the IDLE state, so
if the master is to resume the data requests, it must re-
generate the START condition.
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