參數(shù)資料
型號: V53C16256L
廠商: Mosel Vitelic, Corp.
英文描述: 3.3 Volt 256K x 16 Fast Page Mode CMOS Dynamic RAM(3.3V 256Kx16快速頁面模式CMOS動態(tài)RAM)
中文描述: 3.3伏256K × 16快速頁面模式的CMOS動態(tài)RAM(3.3 256Kx16快速頁面模式的CMOS動態(tài)內(nèi)存)
文件頁數(shù): 17/20頁
文件大?。?/td> 148K
代理商: V53C16256L
17
MOSEL V ITELIC
V53C16256L
V53C16256L Rev. 2.5 February 1999
normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the
WE low transition to allow Data In Setup Time (t
DS
) to be satisfied.
Power-On
After application of the V
CC
supply, an initial pause of 200
m
s is required followed by a minimum of 8 ini-
tialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required
after extended periods of bias without clocks (greater than the Refresh Interval).
During Power-On, the V
CC
current requirement of the V53C16256L is dependent on the input levels of RAS
and CAS. If RAS is low during Power-On, the device will go into an active cycle and I
CC
will exhibit current
transients. It is recommended that RAS and CAS track with V
CC
or be held at a valid V
IH
during Power-On
to avoid current surges.
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V53C16256 256K x 16 FAST PAGE MODE CMOS DYNAMIC RAM
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V53C16258H HIGH PERFORMANCE 256K X 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH
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