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參數(shù)資料
| 型號： | V53C364165A |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 3.3 Volt 4M X 16 EDO Page Mode CMOS Dynamic RAM(3.3V 4Mx16 EDO頁面模式CMOS動態(tài)RAM) |
| 中文描述： | 3.3伏特4米× 16 EDO公司頁面模式的CMOS動態(tài)RAM（3.3 4Mx16 EDO公司頁面模式的CMOS動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 167K |
| 代理商： | V53C364165A |
9
V53C364165A Rev. 0.2 September 1998
MOSEL V ITELIC
V53C364165A
15.
t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If t
WCS
> t
WCS
(min.), the cycle is an early write cycle and the I/O pin will remain open-
circuit (high impedance) through the entire cycle; if t
RWD
> t
RWD (min.)
, t
CWD
> t
CWD (min.)
, t
AWD
> t
AWD (min.)
and
t
CPWD
> t
CPWD (min.)
, the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If
neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate.
16.
These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in Read-
Modify-Write cycles.
17)
When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh
interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit
from Self Refresh.
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