參數(shù)資料
型號(hào)： V59C1G01808QBLF-19A
廠商： PROMOS TECHNOLOGIES INC
元件分類： DRAM
英文描述： DDR DRAM, PBGA68
封裝： ROHS COMPLIANT, FBGA-68
文件頁數(shù)： 14/80頁
文件大?。?/td> 971K
代理商： V59C1G01808QBLF-19A
21
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
V59C1G01(408/808)QB Rev. 1.1 December 2008
ODT Timing for Active / Standby (Idle) Mode and Standard Acti ve Power-Do wn Mode
ODT Timing for Precha rge Power-Down and Lo w Power Power -Down Mode
1) Both ODT to Power Down Entry and Exit Latency timing parameter tANPD and tAXPD are met, therefore Non-Power Down
Mode timings have to be applied.
2) ODT turn-on time (tAON,min) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on
time max. (tAON,max) is when the ODT resistance is fully on. Both are measured from tAOND.
3) ODT turn off time min. ( tAOF,min) is when the device starts to turn off the ODT resistance.ODT turn off time max. (tAOF,max) is
when the bus is in high impedance. Both are measured from tAOFD.
CKE
DQ
ODT1
ODT
CK, CK
T0
Rtt
t
IS
t
IS
tAON(min)
tAON(max)
tAOF(max)
tAOF(min)
t
IS
tAOND
tAOFD
tANPD
tAXPD
t
IS
T-3
T-1
T-2
T-6
T-4
T-5
T-n
1) Both ODT to Power Down Entry and Exit Latencies tANPD and tAXPD are not met, therefore Power-Down Mode timings have to
be applied.
CKE
DQ
ODT
ODT2
CK, CK
t
IS
t
IS
tAOFPD,min
Rtt
tAONPD,min
tAOFPD,max
tAONPD,max
tANPD
tAXPD
T0
T1
T-1
T-2
T-3
T-5
T-4
T-6
T-7
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