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| 型號： | V59C1G01808QBLF-19A |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM, PBGA68 |
| 封裝： | ROHS COMPLIANT, FBGA-68 |
| 文件頁數(shù)： | 15/80頁 |
| 文件大?。?/td> | 971K |
| 代理商： | V59C1G01808QBLF-19A |
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V59C1G01(408/808)QB Rev. 1.1 December 2008
ProMOS TECHNOLOGIES
V59C1G01(408/808)QB
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge
of the clock. The bank addresses of BA0 - BA 2 are used to select the desired bank. The row addresses A0
through A13 are used to determine which row to activate in the selected bank for x4 and x8 organized compo-
nents.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or
without Auto-Precharge) on the following clock cycle. If a R/W command issued to a bank that has not
satisfied the tRCDmin specification, then additive latency must be programmed into the device to delay
the R/W command which is internally issued to the device. The additive latency value must be chosen
to assure tRCDmin is satisfied.
Additive latencies of 0,1,2,
are supported. Once a bank has
been activated it must be precharged before another Bank Activate command can be applied to the sam
bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum tim
interval between successive Bank Activate commands to the same bank is determined (tRC). The minimum
time interval between Bank Active commands, to any other bank, is the Bank A to Bank B delay time (tRRD).
3, 4,5 and 6
The Bank Active command must be applied before any Read or Write operation can be executed.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2
Address
Command
T0
T2
T1
T3
T4
Col. Addr.
Bank A
Row Addr.
Bank B
Col. Addr.
Bank B
Internal RAS-CAS delay tRCDmin.
Bank A to Bank B delay tRRD.
Activate
Bank B
Read A
Posted CAS
Activate
Bank A
Read B
Posted CAS
Read A
Begins
Row Addr.
Bank A
Addr.
Bank A
Precharge
Bank A
Addr.
Bank B
Precharge
Bank B
Row Addr.
Bank A
Activate
Bank A
tRP Row Precharge Time (Bank A)
tRC Row Cycle Time (Bank A)
Tn
Tn+1
Tn+2
Tn+3
ACT
RAS-RAS delay tRRD.
tRAS Row Active Time (Bank A)
additive latency AL=2
CK, CK
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