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參數(shù)資料
| 型號(hào)： | V6123 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Programmable 2, 4 and 8 Mux LCD Driver |
| 中文描述： | 數(shù)字可編程2，4和8復(fù)用器LCD驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 1479K |
| 代理商： | V6123 |
10
V6123
Functional Description
Supply Voltage V
LCD
, V
DD
, V
SS
The volt age be ween V
and V
is the sup ply volt age for
the logic and the in er ace. The volt age be ween V
and
V
SS
is the sup ply volt age for the LCD and is used for the
gen er a ion of the in er nal LCD bias level which have a
max mum im ped ance of 30 k
for a volt age from 3 to
8.5 V. With out ex er nal con nec ions to the V1, V2, V3 bias
level in puts, the V6123 can drive most me dium sized LCD
(pixel aera up to 4’000 mm
2
).
For dis plays with a wide vari a ion in pixel sizes, the con
fig u a ion shown in Fig. 12 can give en hanced con rast by
giv ng faster pixel switch ng times. On chang ng the row
po ar ty (see Fig. 7, 8 and 9) the par al el ca pac ors lower
the im ped ance of the bias level gen er a ion to the peak
cur ent, giv ng faster pixel charge times and thus a higher
RMS “on” value. A higher RMS “on” value can give better
con rast. If for a given LCD size and op er at ng volt age, the
"off" pix els ap pear
"on", or there is poor con rast, then an
ex er nal bias level gen er a ion cir cuit can be used with the
V6123. An ex er nal bias gen er a ion cir cuit can lower the
bias level im ped ance and hence im prove the LCD con -
trast (see Fig. 11). The op i mum val ues of R, Rx and C,
vary ac cord ng to the LCD size used and V
. They are
best de er mined through ac ual ex per men a ion with the
LCD.
For LCD with very large av er age pixel area (eg. up to
10’000 mm
2
), the bias level con ig u a ion shown in Fig. 13
should be used.
When V6123 are cas caded, con nect the V1, V2 and V3
bias in puts as shown in Fig. 10. The pixel load is av er
aged across all the cas caded driv ers. This will give en -
hanced dis play con rast as the ef ec ive bias level source
im ped ance is the par al el com bi na ion of the to al num
ber of driv ers. For ex am ple, if two V6123 are cas caded as
shown in Fig. 10, then the max mum bias level im ped
ance be comes 15 k
for a V
volt age from 3 to 8.5 V.
Ta ble 8 shows the re a ion ship be ween V1, V2 and V3 for
the mul i plex rates 2, 4 and 8. Note that V
> V1 > V2 >
V3 for the V6123 2 and 8 mux pro grammed, and for the
V6123 4 mux pro grammed, V
LCD
> V1 > V2, and V3 = V
SS
.
Data Input / Output
The data in put pin, DI, is used to load se ial data into the
V6123. The se ial data word length is 68 bits. Data is
loaded in in verse nu mer cal or der, the data for bit 68 is
loaded first, the data for bit 1 last. The col umn data bits
are loaded first and then the com mand byte (see Fig. 5).
The data out put pin, DO, is used in cas caded ap pli ca ion
(see Fig. 10). DO trans ers the data to the next cas caded
chip. The data at DO is equal to the data at DI de ayed by
68 clock pe i ods. In or der to cas cade V6123s, the DO of
one chip must be con nected to DI of the fol ow ng chip
(see Fig. 10).
In cas caded ap pli ca ions the data for the last V6123 (the
one that does not have DO con nected) must be loaded
first and the data for the first V6123 (it is DI con nected to
the pro ces sor) loaded last.
The dis play RAM word length is 60 bits (see Fig. 6). Each
LCD row has a cor e spond ng dis play RAM ad dress
which pro vides the col umn data (on or off) when the row
is se ected (on). When down load ng data to the V6123,
any dis play RAM ad dress can be cho sen. Dis play RAM
ad dress is given by com mand bits 3 to 5. Bit 6 forces all
col umn out puts at 0L (dis play OFF). Bit 7 forces all col
umn out puts at 1L (dis play ON). If bit 7 (SET) and bit 6
(BLANK) are both ac ive, the ini ial za ion func ion is ac i
vated. This func ion is used to syn chro nize the chip at row
one. The com mand bit 2 (COL) de ines the V6123 as a
row and col umn driver or col umn driver only. The V6123
func ions as row and col umn driver while the bit 2 (COL)
is in ac ive. When ac ive, the bit 2 configures the V6123 to
func ion as col umn driver only. The for mer row out puts
func ion as col umn out puts. In cas caded ap pli ca ions,
one V6123 should be used in the row and col umn con ig
u a ion (COL in ac ive) and the rest as pure col umn driv
ers (COL ac ive) (see Fig. 10). Note when cas cad ng
V6123s never cas cade one mux mode num ber with an -
other. If a V6123 8 mux pro grammed is used to drive the
rows, then only V6123 8 mux pro grammed can be cas -
caded with it.
The com mand bits, bit 1 and bit 0, de ine the mux mode
(see Fig. 5).
CLK Input
The clock in put is used to clock the DI se ial data into the
shift reg s er, to latch the data from the shift reg s er into
the RAM .
Af er load ng data into the shift reg s er, the clock has to
stay 0 logic dur ng T
.
Af er T
STR
pulse, the data are latched into the RAM.
FR Input / Output
The frame fre quency is re al zed by an in er nal RC os cil a
tor with a typ cal value of 55 Hz. The in er nal row fre
quency changes with the num ber of rows (F
row
= 55 x n,
where n = 2, 4 or 8).
When bit 2 (COL) is in ac ive (row and col umn driver), the
frame fre quency is given by the in er nal os cil a or. This
fre quency can also be used at FR out put to drive
casecaded V6123.
When bit 2 (COL) is ac ive (col umn driver only), the frame
fre quency is ex er nal then the fre quency is given by the
row and col umn driver di ectly to the FR in put. In cas
caded ap pli ca ions, the row and col umn driver (FR, out
put) give the frame fre quency to all the cas caded chip
(FR, in put).
Driver Outputs S1 to S60
There are 60 LCD driver out puts on the V6123. When bit 2
(COL) is in ac ive, the out puts S1 to Sn func ion as row
driv ers and the out puts S(n+1) to S60 func ion as col umn
driv ers. Where n is the V6123 mux mode num ber (2, 4 or
8).
When bit 2 (COL) is ac ive, all 60 out puts func ion as col
umn driv ers (see Ta ble 6). There is a one to one re a ion
ship be ween the dis play RAM and the LCD driver
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