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參數(shù)資料
| 型號： | V6123 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digitally Programmable 2, 4 and 8 Mux LCD Driver |
| 中文描述： | 數(shù)字可編程2，4和8復(fù)用器LCD驅(qū)動器 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 1479K |
| 代理商： | V6123 |
Absolute Maximum Ratings
Parameter
Supply voltage range
LCD supply voltage range
Voltage at DI, DO, CLK, FR
Voltage at V1 to V3, S1 to S60
Storage temperature range
PElectrostatic discharge max.
to MIL-STD-883C method 3015
Maximum soldering conditions
Symbol
V
DD
V
LCD
V
LOGIC
V
DISP
T
STO
Conditions
-0.3 V to 9 V
-0.3 V to 10 V
-0.3 V to V
DD
+0.3 V
-0.3 V to V
+0.3 V
-65 to +150 °C
V
Smax
T
Smax
1000 V
250 °C x 10 s
Ta ble 1
Stresses above these listed max mum rat ngs may cause
per ma nent dam age to the de vice. Ex po sure be yond
spec ied op er at ng con di ions may af ect de vice re i abil
ity or cause mal unc ion.
Handling Procedures
This de vice has built-in pro ec ion against high static volt
ages or elec ric fields; how ever, anti-static pre cau ions
must be taken as for any other CMOS com po nent. Un ess
oth er wise spec ied, proper op er a ion can only oc cur
when all ter mi nal volt ages are kept within the sup ply volt
age range. Un used in puts must al ways be tied to a de -
fined logic volt age level.
Operating Conditions
Parameter
Symbol Min. Typ.Max. Unit
Operating temperature
Logic supply voltage
LCD supply voltage
T
A
V
DD
V
LCD
-40
2
2
+85
6
8.5
°C
V
V
5
5
Ta ble 2
2
V6123
Electrical Characteristics
V
DD
= 5 V ± 10%, V
LCD
= 2 to 8.5 V and T
A
= -40 to +85 °C, un ess oth er wise spec ied
Parameter
Symbol Test Conditions
Min.
Typ.
Max.
Units
Dynamic supply current
Dynamic supply current
Dynamic supply current
Dynamic supply current
I
LCD
I
DD
I
DD
I
DD
See note
1)
See note
1)
at T
A
= 25 °C
See note
1)
See note
2)
175
29
29
285
250
35
50
350
μA
μA
μA
μA
Control Signals DI, CLK, FR
Input leakage
Input capacitance
Low level input voltage
High level input voltage
I
IN
C
IN
V
IL
V
IH
0 < V
< V
DD
at T
A
= 25 °C
1
8
100
nA
pF
V
V
0
0.8
V
DD
2.0
Data Output DO
High level output voltage
Low level output voltage
V
OH
V
OL
I
H
= 2 mA
I
L
= 2 mA
2.4
V
V
0.4
Driver Outputs S1 … S60
Driver impedance
4)
Driver impedance
4)
Driver impedance
4)
Bias impedance V1, V2, V3
5)
Bias impedance V1, V2, V3
5)
Bias impedance V1, V2, V3
5)
DC output component
R
OUT
R
OUT
R
OUT
R
BIAS
R
BIAS
R
± VDC
I
OUT
= 10 μA, V
LCD
= 7 V
I
OUT
= 10 μA, V
LCD
= 3 V
I
OUT
= 10 μA, V
LCD
= 2 V
I
OUT
= 10 μA, V
LCD
= 7 V
I
OUT
= 10 μA, V
LCD
= 3 V
I
= 10 μA, V
= 2 V
see Tables 4a and 4b, V
LCD
= 5 V
1
1.5
3.5
k
k
k
k
k
k
mV
2.6
7
18
20
24
15
24
27
50
1)
All out puts open, DI and CLK at V
, FR = 400 Hz, all other in puts at V
DD
Ta ble 3
2)
All out puts open, DI at V
, FR = 400 Hz, f
CLK
= 1 MHz
3)
All out puts open, all in puts at V
DD
4)
This is the im ped ance be ween of the volt age bias level pins (V1, V2 or V3) and the out put pins S1 to S60 when a given volt age
bias level is driv ng the out puts (S1 to S60)
5)
This is the im ped ance seen at the seg ment pin. Out puts mea sured one at a time
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