參數(shù)資料
型號: VND5E012AYTR-E
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO36
封裝: ROHS COMPLIANT, SSOP-36
文件頁數(shù): 9/37頁
文件大?。?/td> 924K
代理商: VND5E012AYTR-E
VND5E012AY-E
Electrical specifications
Doc ID 13621 Rev 2
Table 12.
Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test Pulse
Test levels(1)
1.
The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III
IV
1
-75 V
-100 V
5000
pulses
0.5 s
5 s
2 ms, 10
Ω
2a
+37 V
+50 V
5000
pulses
0.2 s
5 s
50
μs, 2 Ω
3a
-100 V
-150 V
1h
90 ms
100 ms
0.1
μs, 50 Ω
3b
+75 V
+100 V
1h
90 ms
100 ms
0.1
μs, 50 Ω
4
-6 V
-7 V
1 pulse
100 ms, 0.01
Ω
5b(2)
2.
Valid in case of external load dump clamp: 40 V maximum referred to ground.
+65 V
+87 V
1 pulse
400 ms, 2
Ω
Table 13.
Electrical transient requirements (part 2)
ISO 7637-2:
2004(E)
Test pulse
Test level results(1)
1.
The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b
III
IV
1C
C
2a
C
3a
C
3b
C
4C
C
5b(2) (3)
2.
Valid in case of external load dump clamp: 40 V maximum referred to ground.
3.
Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
CC
Table 14.
Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
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