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參數(shù)資料
| 型號： | W233 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 178K |
| 代理商： | W233 |
W233
PRELIMINARY
Document #: 38-07250 Rev. *A
Page 10 of 16
Absolute Maximum Ratings
[2]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter
V
DD
, V
IN
T
STG
T
B
T
A
ESD
PROT
Description
Rating
–
0.5 to +7.0
–
65 to +150
–
55 to +125
0 to +70
2 (min.)
Unit
V
°
C
°
C
°
C
kV
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature under Bias
Operating Temperature
Input ESD Protection
DC Electrical Characteristics:
T
A
= 0
°
C to +70
°
C, V
DD
= 3.3V±5%
Parameter
Description
Supply Current
I
DD
3.3V Supply Current
Test Condition
Min.
Typ.
Max.
Unit
CPUT0_F, CPUC0_F,
CPU_CS =100 MHz
Outputs Loaded
[3]
CPUT0_F, CPUC0_F,
CPU_CS =100 MHz
Outputs Loaded
[3]
260
mA
I
DD
2.5V Supply Current
25
mA
Logic Inputs
V
IL
V
IH
I
IL
I
IH
Clock Outputs
V
OL
V
OH
V
OL
Input Low Voltage
Input High Voltage
Input Low Current
[4]
Input High Current
[4]
GND
–
0.3
2.0
0.8
V
V
μA
μA
V
DD
+ 0.3
–
25
10
Output Low Voltage
Output High Voltage
Output Low Voltage
I
OL
= 1 mA
I
OH
=
–
1 mA
Termination to V pull-up
(external)
50
mV
V
V
3.1
0
CPU_CS,
CPUT0_F,
CPUC0_F
CPU_CS,
CPUT0_F,
CPUC0_F
PCI0:6, PCI_F
REF0:2
48 MHz
24 MHz
SDRAM0:5,
SDRAM_F
PCI0:6, PCI_F
REF0:2
48 MHz
24 MHz
SDRAM0:5,
SDRAM_F
0.3
V
OH
Output High Voltage
Termination to V pull-up
(external)
1.0
1.2
V
I
OL
Output Low Current
V
OL
= 1.5V
V
OL
= 1.5V
V
OL
= 1.5V
V
OL
= 1.5V
V
OL
= 1.5V
70
50
50
50
70
110
70
70
70
110
135
100
100
100
135
mA
mA
mA
mA
mA
I
OH
Output High Current
V
OH
= 1.5V
V
OH
= 1.5V
V
OH
= 1.5V
V
OH
= 1.5V
V
OH
= 1.5V
70
50
50
50
70
110
70
70
70
110
135
100
100
100
135
mA
mA
mA
mA
mA
Notes:
2.
3.
4.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
All clock outputs loaded with 6" 60
transmission lines with 20-pF capacitors.
W233 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.
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