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參數(shù)資料
| 型號(hào)： | W233 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 178K |
| 代理商： | W233 |
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W233
PRELIMINARY
Document #: 38-07250 Rev. *A
Page 4 of 16
Overview
The W233 was developed as a single-chip device to meet the
clocking needs of VIA K7 core logic chip sets. In addition to the
typical outputs provided by a standard FTG, the W233 adds a
seventh output buffer, supporting SDRAM DIMM modules in
conjunction with the chipset.
Cypress
’
s proprietary spread spectrum frequency synthesis
technique is a feature of the CPU and PCI outputs. When en-
abled, this feature reduces the peak EMI measurements of not
only the output signals and their harmonics, but also of any
other clock signals that are properly synchronized to them.
Functional Description
I/O Pin Operation
Pins 4, 5, 22, 23, and 46 are dual-purpose l/O pins. Upon
power-up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power-
up, the logic state of each pin is latched and the pins become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10-k
“
strapping
”
resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to
“
0,
”
connection to V
DD
sets a latch to
“
1.
”
Figure 1
and
Figure 2
show two suggested methods for strapping resistor
connections.
Upon W233 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the five I/O pins (4, 5,
22, 23, 46) are three-stated, allowing the output strapping re-
sistor on the l/O pins to pull the pins and their associated ca-
pacitive clock load to either a logic HIGH or LOW state. At the
end of the 2-ms period, the established logic
“
0
”
or
“
1
”
condi-
tion of the l/O pin is latched. Next the output buffer is enabled
converting the l/O pins into operating clock outputs. The 2-ms
timer starts when V
DD
reaches 2.0V. The input bits can only be
reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of clock outputs is <40
(nominal), which is minimally
affected by the 10-k
strap to ground or V
DD
. As with the se-
ries termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or V
DD
should be kept less than two inches in length
to prevent system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, the specified output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W233
V
DD
Clock Load
R
10 k
Output
Buffer
(Load Option 1)
10 k
(Load Option 0)
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
Output
Low
Q
D
W233
V
DD
Clock Load
R
10 k
Output
Buffer
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Figure 2. Input Logic Selection Through Jumper Option
Resistor Value R
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