參數(shù)資料
型號: W234
英文描述: Clocks and Buffers
中文描述: 時鐘和緩沖器
文件頁數(shù): 1/14頁
文件大小: 160K
代理商: W234
Dual Direct Rambus Clock Generator
W234
Cypress Semiconductor Corporation
Document #: 38-07232 Rev. *B
3901 North First Street
San Jose
CA 95134
Revised December 21, 2002
408-943-2600
Features
Differential clock source for Direct Rambus
memory
subsystem for up to 1.6-Gb/s serial data transfer rate
Provide synchronization flexibility: the Rambus
Chan-
nel can optionally be synchronous to an external sys-
tem or processor clock
Power managed output allows Rambus Channel clock
to be turned off to minimize power consumption for
mobile applications
Works with Cypress CY2210-2, CY2210-3, CY2215,
W133, W158, W159, W161, and W167B to support Intel
architecture platforms
Low-power CMOS design packaged in a 28-pin, 173-mil
TSSOP package
Overview
The Cypress W234 provides dual channel differential clock
signals for a Direct Rambus memory subsystem. It includes
signals to synchronize the Direct Rambus Channel clock to an
external system clock but can also be used in systems that do
not require synchronization of the Rambus clock.
Key Specifications
Supply Voltage: ................................... V
DD
= 3.3V ± 0.165V
Operating Temperature: ................................... 0
°
C to +70
°
C
Input Threshold: ..................................................1.5V typical
Maximum Input Voltage:.......................................V
DD
+ 0.5V
Maximum Input Frequency:.....................................100 MHz
Output Duty Cycle: .................................. 40/60% worst case
Output Type:........................... Rambus signaling level (RSL)
Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.
Intel is a registered trademark of Intel Corporation.
Block Diagram
Pin Configuration
PLL
Phase
Alignment
MULT0:2
REFCLK
Logic
Logic
Test
STOP#
S0:2
CLK0
CLK0#
Phase
Alignment
PWR_DWN#
CLK1
CLK1#
PCLKM0
SYNCLKN0
PCLKM1
SYNCLKN1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDIR
REFCLK
VDD
SYNCLKN0
PCLKM0
GND
VDD
GND
SYNCLKN1
PCLKM1
VDD
VDDIPD
STOP#
PWR_DWN#
28
27
26
25
24
23
22
21
20
19
18
17
16
15
S0
S1
S2
GND
CLK0#
CLK0
VDD
VDD
CLK1
CLK1#
GND
MULT0
MULT1
MULT2
Logic
Output
Output
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