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參數(shù)資料
| 型號： | W238-02 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 182K |
| 代理商： | W238-02 |
W238-02
Document #: 38-07103 Rev. *A
Page 7 of 18
Power Down Control
W238 provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
Notes:
7.
8.
9.
10. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W238.
Table 3. W238 Maximum Allowed Current
W238
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
V
= 2.625V
All static inputs = V
DDQ3
or V
SS
100
μ
A
Max. 3.3V supply consumption
Max. discrete cap loads
V
= 3.465V
All static inputs = V
DDQ3
or V
SS
500
μ
A
Powerdown Mode
(PWRDWN# = 0)
Full Active 66 MHz
FSEL1:0 = 00 (PWRDWN# =1)
Full Active 100 MHz
FSEL1:0 = 01 (PWRDWN# =1)
Full Active 133 MHz
FSEL1:0 = 10, 11 (PWRDWN# =1)
30 mA
280 mA
40 mA
280 mA
50 mA
400 mA
1
2
Center
0ns
25ns
50ns
75ns
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 7. W238 PWRDWN# Timing Diagram
[7, 8, 9, 10]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W238 | Clocks and Buffers |
| W23C4096-12 | x8 ROM (Mask Programmable) |
| W23C4096-15 | x8 ROM (Mask Programmable) |
| W23C4096-20 | x8 ROM (Mask Programmable) |
| W23C8192-12 | x8 ROM (Mask Programmable) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W238E32A | 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Replaced by W238-E1-7 |
| W23C4096-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
| W23C4096-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
| W23C4096-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
| W23C8192-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 ROM (Mask Programmable) |
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