參數(shù)資料
型號(hào)： W3H32M64EA-533SBC
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 32M X 64 DDR DRAM, PBGA208
封裝： 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 1057K
代理商： W3H32M64EA-533SBC
24
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2010 2010 White Electronic Designs Corp. All rights reserved
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
W3H32M64EA-XSBX
TABLE 12 – AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
Parameter
Symbol
667Mbs CL5
533Mbs CL4
400Mbs CL3
Unit
Min
Max
Min
Max
Min
Max
Clock
Clock cycle time
CL=5
tCK(4)
3,000
8,000
ps
CL=4
tCK(4)
3,750
8,000
3,750
8,000
5,000
8,000
ps
CL=3
tCK(3)
5,000
8,000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.48
0.52
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN (tCH,
tCL)
MIN (tCH,
tCL)
MIN (tCH,
tCL)
ps
Data
DQ output access time from CK/CK#
tAC
-550
+650
-550
+650
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
tAC(MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC(MN) tAC(MAX) tAC(MN) tAC(MAX) tAC(MN) tAC(MAX)
ps
DQ and DM input setup time relative to DQS
tDS
400
450
ps
DQ and DM input hold time relative to DQS
tDH
500
450
ps
DQ and DM input pulse width (for each input)
tDIPW
0.35
tCK
Data hold skew factor
tQHS
400
450
ps
DQ-DQS hold, DQS to rst DQ to go nonvalid, per access
tQH
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH
- tDQSQ
tQH
- tDQSQ
tQH
- tDQSQ
ns
Data
Strobe
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-550
+650
-550
+650
-600
+600
ps
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
O DQS-DQ skew, DOS to last DQ valid, per group, per access
tDQSQ
300
350
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
000
ps
DQS write preamble
tWPRE
0.25
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to rst DQS latching transition
WL-
TDQSS
WL+
TDQSS
WL-
TDQSS
WL+
TDQSS
WL-
TDQSS
WL+
TDQSS
tCK
Positive DQs latch edge to associated edge
tOQSS
-0.18
+0.18
-0.25
+0.25
-0.25
+0.25
tCK
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