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參數(shù)資料
| 型號： | W3H32M64EA-533SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 64 DDR DRAM, PBGA208 |
| 封裝： | 16 X 20 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 1057K |
| 代理商： | W3H32M64EA-533SBC |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2010 2010 White Electronic Designs Corp. All rights reserved
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
W3H32M64EA-XSBX
15
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2010 2010 White Electronic Designs Corp. All rights reserved
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
W3H32M64EA-XSBX
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes: 1–3 apply to the entire table
Function
CKE
CS#
RAS#
CAS#
WE#
BA2
BA0
An
A11
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
LOAD MODE
H
LLLL
BA
OP Code
4, 6
REFRESH
H
L
H
XXXX
SELF-REFRESH Entry
H
L
H
XXXX
SELF-REFRESH Exit
LH
H
XXX
XXXX
4, 7
L
HHH
Single bank precharge
HH
L
H
L
BA
X
L
X
6
All banks PRECHARGE
HH
L
H
L
X
H
X
Bank activate
H
L
H
BA
Row Address
4
WRITE
HH
L
H
L
BA
Column
Address
L
Column
Address
4, 5, 6, 8
WRITE with auto precharge
HH
L
H
L
BA
Column
Address
H
Column
Address
4, 5, 6, 8
READ
H
LH
BA
Column
Address
L
Column
Address
4, 5, 6, 8
READ with auto precharge
H
LH
BA
Column
Address
H
Column
Address
4, 5, 6, 8
NO OPERATION
H
X
L
H
XXXX
Device DESELECT
H
X
H
XXXXXXX
POWER-DOWN entry
HL
H
XXX
XXXX
9
L
HHH
POWER-DOWN exit
LH
H
XXX
XXXX
9
L
HHH
Notes:
1.
All DDR2 SDRAM commands are dened by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2.
The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.
3.
“X” means “H or L” (but a dened logic level) for valid IDD measurements.
4.
BA2 is only applicable for densities ≥1Gb.
5.
An n is the most signicant address bit for a given density and conguration. Some larger address bits may be “Don’t Care” during column addressing, depending on density and
conguration.
6.
Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD MODE command selects which mode register is programmed.
7.
SELF REFRESH exit is asynchronous.
8.
Burst reads or writes at BL = 4 cannot be terminated or interrupted.
9.
The power-down mode does not perform any REFRESH operations. The duration of powerdown is limited by the refresh requirements outlined in the AC parametric section.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H32M64E-ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M64E-ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M64E-ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M64E-ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H32M64E-SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:32M x 64 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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