- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄245692 > W3HG256M72AER403AD6MG (WHITE ELECTRONIC DESIGNS CORP) 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 PDF資料下載
參數(shù)資料
| 型號： | W3HG256M72AER403AD6MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, RDIMM-240 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG256M72AER403AD6MG |
W3HG256M72AER-AD6
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (Continued)
AC CHARACTERISTICS
SYMBOL
806
665
534
403
UNIT
Notes
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data
Strobe
DQS read preamble
tRPST
TBD
TDB
0.4
0.6
0.4
0.6
0.4
0.6
tCK
33, 34,
37, 43
DQS write preamble setup time
tWPRES
TBD
TDB
0
ps
12, 13
DQS write preamble
tWPRE
TBD
TDB
0.35
0.25
tCK
37
DQS write postamble
tWPST
TBD
TDB
0.4
0.6
0.4
0.6
0.4
0.6
tCK
11, 37
Write command to rst DQS
latching transition
tDQSS
TBD
TDB
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
37
Command
and
Address
Address and control input
pulse width for each input
tIPW
TBD
TDB
0.6
tCK
37
Address and control input
setup time
tISa
TBD
TDB
400
600
ps
6, 19
Address and control input
hold time
tIHa
TBD
TDB
400
600
ps
Address and control input
setup time
tISb
TBD
TDB
200
250
350
ps
Address and control input
hold time
tIHb
TBD
TDB
275
375
475
ps
CAS# to CAS# command
delay
tCCD
TBD
TDB
222
tCK
37
Active to Active (same bank)
command
tRC
TBD
TDB
55
ns
31, 37
Active bank a to Active b bank
command
tRRD
TBD
TDB
7.5
ns
25, 37
Active to Read or Write delay
tRCD
TBD
TDB
15
ns
37
Four Bank Activate period
tFAW
TBD
TDB
37.5
ns
28, 37
Active to precharge command
tRAS
TBD
TDB
40
70,000
40
70,000
40
70,000
ns
18, 31,
37
Internal Read to precharge
command delay
tRTP
TBD
TDB
7.5
ns
21, 25,
37
Write recovery time
tWR
TBD
TDB
15
ns
25, 37
Auto precharge write recovery
and precharge time
tDAL
TBD
TDB
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
20
Interval Write to Read
command delay
tWTR
TBD
TDB
7.5
10
ns
25, 37
Precharge command period
tRP
TBD
TDB
15
ns
29, 37
Precharge All command period
tRPA
TBD
TDB
tRP+tCK
ns
29
Load Mode command cycle
time
tMRD
TBD
TDB
222
tCK
37
CKE low to CK,CK#
uncertainty
tDELAY
TBD
tIS + tCK + tIH
ns
26
NOTE:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WED3DG6435V75JD1I-QG | 32M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA144 |
| W7MG21M32SVB120BNC | 2M X 32 FLASH 3.3V PROM MODULE, 120 ns, SMA80 |
| W3E232M16S-250STI | 64M X 16 DDR DRAM, 0.7 ns, PDSO66 |
| W3EG64128S265D3M | 128M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG64128S403JD3S | 128M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG264M72EER403AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER534AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER665AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG264M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。