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參數(shù)資料
| 型號(hào)： | W3HG256M72AER403AD6MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, RDIMM-240 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG256M72AER403AD6MG |
W3HG256M72AER-AD6
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2007
Rev. 1
Notes
1.
All voltages referenced to VSS
2.
Tests for AC timing, ICC, and electrical AC and DC characteristics
may be conducted at nominal reference/supply voltage levels, but
the related specications and device operation are guaranteed
for the full voltage range specied. ODT is disabled for all
measurements that are not ODT-specic.
3.
Outputs measured with equivalent load:
4.
AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.0V in
the test environment and parameter specications are guaranteed
for the specied AC input levels under normal use conditions.
The slew rate for the input signals used to test the device is 1.0
V/ns for signals in the range between VIL(AC) and VIH(AC). Slew
rates other than 1.0 V/ns may require the timing parameters to be
derated as specied.
5.
The AC and DC input level specications are as dened in the
SSTL_18 standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level and will remain in
that state as long as the signal does not ring back above [below]
the DC input LOW [HIGH] level).
6.
There are two sets of values listed for Command/Address: tISa,
tIHa and tISb, tIHb. The tISa, tIHa values (for reference only)
are equivalent to the baseline values of tISb, tIHb at VREF when
the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the
JEDEC-dened values, referenced from the logic trip points. tISb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a
falling signal, while tIHb is referenced from VIL(DC) for a rising
signal and VIH(DC) for a falling signal. If the Command/Address
slew rate is not equal to 1 V/ns, then the baseline values must be
derated.
7.
The values listed are for the differential DQS strobe (DQS and
DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each
signal). There are two sets of values listed: tDSa, tDHa and tDSb,
tDHb. The tDSa, tDHa values (for reference only) are equivalent
to the baseline values of tDSb, tDHb at VREF when the slew rate
is 2 V/ns, differentially. The baseline values, tDSb, tDHb, are the
JEDEC-dened values, referenced from the logic trip points. tDSb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a
falling signal, while tDHb is referenced from VIL(DC) for a rising
signal and VIH(DC) for a falling signal. If the differential DQS
slew rate is not equal to 2 V/ns, then the baseline values must
be derated. If the DQS differential strobe feature is not enabled,
then the DQS strobe is single-ended, the baseline values not
applicable, and timing is not referenced to the logic trip points.
Single-ended DQS data timing is referenced to DQS crossing
VREF.
8.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specic voltage level, but specify when the device output is no
longer driving (tHZ) or begins driving (tLZ).
9.
This maximum value is derived from the referenced test load. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
Output
(VOUT)
Reference
Point
25
VTT = VCCQ/2
10.
tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX)
condition.
11.
11. The intent of the “Don’t Care” state after completion of the
postamble is that the DQS-driven signal should either be HIGH,
LOW, or High-Z, and that any signal transition within the input
switching region must follow valid input requirements. That is,
if DQS transitions HIGH (above VIH[DC] MIN), then it must not
transition LOW (below VIH[DC]) prior to tDQSH (MIN).
12.
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
13.
1. It is recommended that DQS be valid (HIGH or LOW) on or
before the WRITE command. The case shown (DQS going from
High-Z to logic LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in progress, DQS
could be HIGH during this time, depending on tDQSS.
14.
The refresh period is 64ms (commercial) or 32ms (industrial). This
equates to an aver-age refresh rate of 7.8125s (commercial) or
3.9607s (industrial). However, a REFRESH command must be
asserted at least once every 70.3s or tRFC (MAX). To ensure
all rows of all banks are properly refreshed, 8,192 REFRESH
commands must be issued every 64ms (commercial) or 32ms
(industrial).
15.
Referenced to each output group: x4 = DQS with DQ0–DQ3; x8
= DQS with DQ0–DQ7; x16 = LDQS with DQ0–DQ7; and UDQS
with DQ8–DQ15.
16.
CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if
measured differentially).
17.
The data valid window is derived by achieving other specications:
tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
18.
READs and WRITEs with auto precharge are allowed to be
issued before tRAS (MIN) is satised since tRAS lockout feature is
supported in DDR2 SDRAM.
19.
VIL/VIH DDR2 overshoot/undershoot.
20.
1. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an
integer, should be rounded up to the next integer. tCK refers to the
application clock period; nWR refers to the tWR parameter stored
in the MR[11, 10, 9]. For example, -37E at tCK = 3.75ns with tWR
programmed to four clocks would have tDAL = 4 + (15ns/3.75ns)
clocks = 4 + (4) clocks = 8 clocks..
21.
1. The minimum internal READ to PRECHARGE time. This is the
time from the last 4-bit prefetch begins to when the PRECHARGE
command can be issued. A 4-bit prefetch is when the READ
command internally latches the READ so that data will output CL
later. This parameter is only applicable when tRTP / (2 x tCK) > 1,
such as frequencies faster than 533 MHz when tRTP = 7.5ns. If tRTP
/ (2 x tCK) 1, then equation AL + BL/ 2 applies. tRAS (MIN) also
has to be satised as well. The DDR2 SDRAM will automatically
delay the internal PRECHARGE command until tRAS (MIN) has
been satised.
22.
1. Operating frequency is only allowed to change during self
refresh mode, precharge power-down mode, or system reset
condition. SSC allows for small deviations in operating frequency,
provided the SSC guidelines are satised.
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