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參數(shù)資料
| 型號(hào)： | W530H |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 184K |
| 代理商： | W530H |
Frequency Multiplying, Peak Reducing EMI Solution
W530
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 22, 2000
Features
Cypress PREMIS family offering
Generates an EMI optimized clocking signal at the out-
put
Selectable output frequency range
Single 1.25%, 2.5%, 5% or 10% down or center spread
output
Integrated loop filter components
Operates with a 3.3 or 5V supply
Low power CMOS design
Available in 20-pin SSOP (Small Shrunk Outline
Package)
Key Specifications
Supply Voltages:.........................................V
DD
= 3.3V±0.3V
or V
DD
= 5V±10%
Frequency range: ............................13 MHz
≤
F
in
≤
120 MHz
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: .................................40/60% (worst case)
PREMIS is a trademark of Cypress Semiconductor.
W
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
X1
X2
AVDD
MW0^
STOP^
OR1^
NC
GND
REFOUT
VDD
GND
IR1*
IR2*
SSOUT
MW1*
GND
14
13
15
11
12
VDD
MW2^
OR2*
SSON#^
Simplified Block Diagram
Pin Configuration
SSOP
Spread Spectrum
Output
W530
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W530
(EMI suppressed)
3.3V or 5.0V
Input
X1
X2
X1
Note:
1.
Pins marked with ^ are internal pull-down resistors
with weak 250
.
Pins marked with * are internal
pull-up resistors with weak 250
.
[1]
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