參數(shù)資料
型號(hào): W65C134S8PL-8
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁(yè)數(shù): 12/60頁(yè)
文件大?。?/td> 711K
代理商: W65C134S8PL-8
WESTERN DESIGN CENTER
W65C134S
March 1, 2000
7
1.7
Interrupt Flag Registers (IFR1,IFR2) ($002C,$0008)
1.7.1
A bit of these registers is set to a "1" in response to a signal from a source. Sources specified as
level-triggered assert the corresponding IFR bit if an edge occurs and is held to a "1" as long as the
IRQxB input is held low. Sources specified as edge-triggered assert the corresponding IFR bit upon
and only upon transition to the specified polarity. Note that changes for edge-triggered bits are
asynchronous with PHI2.
1.7.1.1
Read of IFR1 and IFR2
A read from an IFR register transfers its value to the internal data bus.
1.7.1.2
Write to IFR1 and IFR2
A write of a "1" to any bits of these registers disasserts those bits but has no further
effect when execution of that write instruction is completed; that is, the bit is reset by a
pulse but not held reset. A write of a "0" to any bits of these registers has no effect.
1.7.1.3
Interrupt Priority
If more than one bit of the Interrupt Flag Registers are set to a "1" and enabled, the
vector corresponding to the highest bit number asserted is used. For example, if both the
IFR10 and IFR23 were asserted and enabled, then the vector corresponding to IFR23
would be used. For another example, if both the IFR13 and IFR20 were asserted and
enabled, then the vector corresponding to IFR20 would be used.
1.8
Interrupt Enable Registers (IER1,IER2) ($002D,$0009)
IER1 and IER2 are the interrupt enable registers. Reading an IER register reads its contents and puts the
value on the internal data bus. Writing an IER writes a value from the data bus into the register. Setting a bit
in an IER to "1" permits the interrupt corresponding to the same bit in the IFR to cause a processor interrupt.
Also, if the RUN pin was low prior to the interrupt, the pin will go high if BCR3 = 0.
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