參數(shù)資料
型號(hào): W65C134S8PL-8
元件分類: 8位微控制器
英文描述: 8-BIT MICROCONTROLLER
中文描述: 8位微控制器
文件頁數(shù): 20/60頁
文件大?。?/td> 711K
代理商: W65C134S8PL-8
WESTERN DESIGN CENTER
1.11.2 SR0, SR1, SR2, and SR3 Shift Register
W65C134S
March 1, 2000
15
The SR0, SR1, SR2, and SR3 are the four (4) 8-bit shift registers (32-bit shift register) that
are used to transfer messages from one SIB to another SIB on a token passing ring network.
Two to eight SIB's may be connected together (see Figure 1-14 Serial Interface Bus (SIB)
Wiring Diagram for more information).
l
SR3 bits SR37, SR36 and SR35 are the Bus Address Register field of the 32-bit message. All other
bits are command, data, or address fields. Reading SR3 clears the read pending bit SCSR4 and
writing SR0 clears the write pending bit SCSR0.
Figure 1-11 SR0, SR1, SR2, and SR3 Shift Register
1.11.3 The SIB Control and Status Register (SCSR).
The SIB Control and Status Register (SCSR) is used for controlling the SIB and for reading
the status of the SIB. The SCSR is writable only in the sense that a high level can be written
to bits SCSR0, SCSR2, SCSR6 and SCSR7. Together with the STATE Register, it gives
the state of the SIB controller. Bit SCSR6 is used to enable PHI2 as the clock source for
SCLK, bits SCSR4 and SCSR5 are used for receiving, bits SCSR0, SCSR1, and SCSR2 are
used for sending, and STATE is used for both. The SCSR is reset on a system RESET.
1.11.3.0
SCSR0 is the "write pending" control bit of the SCSR. When SCSR0 is set to a
"1" by the on-chip microprocessor, it means that the processor wants to send a
message. It is set on a write of a "1" to SCSR0 from the MPU and reset when
SR0 is written.
SCSR1 is the "master" status bit of SCSR. When SCSR1 gets set to a "1" this
means that the SIB's microprocessor was requesting master (SCSR0 was set to
a "1") just before the last time mastery changed. If CHIN (CHain IN) is high as
well then this device is master when the "token" is passed.
1.11.3.1
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