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參數(shù)資料
| 型號： | W72M64V-XBX |
| 英文描述： | Flash MCP |
| 中文描述： | 閃存MCP的 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 160K |
| 代理商： | W72M64V-XBX |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
W72M64V-X BX
RY/BY
CS, OE
RESET
tRP
tReady
tRH
tReady
tRB
tRP
RY/BY
CS, OE
RESET
AC CHARACTERISTICS – HARDWARE RESET (RESET)
Parameter
Symbol
-100
-120
-150
Unit
Min
Max
Min
Max
Min
Max
RESET Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
t
ready
20
20
20
μs
RESET Pin Low (NOT During Embedded Algorithms)
to Read Mode (See Note)
t
ready
500
500
500
ns
RESET Pulse Width
t
RP
500
500
500
ns
RESET High Time Before Read (See Note)
t
RH
50
50
50
ns
RESET Low to Standby Mode
t
RPD
20
20
20
μs
RY/BY Recovery Time
t
RB
0
0
0
ns
Note:
Not tested.
FIG 4:
RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
FIG 5:
RESET TIMINGS DURING EMBEDDED ALGORITHMS
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| W72M64VK120BM | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
| W72M64VK100BC | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
| W72M64VK100BI | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
| W72M64VK100BM | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
| W72M64VK120BC | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
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