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Preliminary W742C(E)811
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dual-clock slow operation mode, the STOP instruction will disable both the main-oscillator and sub-
oscillator oscillating; To avoid erroneous execution, the NOP instruction should follow the STOP
command.
5.14.1 Stop Mode Wake-up Enable Flag for RC and RD Port (SEF)
The stop mode wake-up flag for port RC and RD is organized as an 8bit binary register (SEF.0 to
SEF.7). Before port RC and RD can be used to exit the stop mode, the content of the SEF must be set
first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:
SEF
w
w
w
4
5
6
w
7
w
w
w
0
1
2
w
3
Note: W means write only.
SEF.0 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.0
SEF.1 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.1
SEF.2 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.2
SEF.3 = 1 Device will exit stop mode when a falling edge signal is applied to pin RC.3
SEF.4 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.0
SEF.5 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.1
SEF.6 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.2
SEF.7 = 1 Device will exit stop mode when a falling edge signal is applied to pin RD.3
5.15 Hold Mode Operation
In hold mode, all operations of the
μ
C cease, except for the operation of the oscillator, Timer, Divider,
and LCD driver. The
μ
C enters hold mode when the HOLD instruction is executed. The hold mode can be
released in one of nine ways: by the action of timer 0, timer 1, divider 0, divider 1, RC port, P1.2(
INT0
),
Serial I/O, P1.3(
INT1
) and RD port. Before the device enters the hold mode, the HEF,HEFD, PEF, and
IEF flags must be set to control the hold mode release conditions. When any of the HCF bits is "1," the
hold mode will be released. Regarding to RC and RD port, PSR0 and PSR1 registers indicate signal
change on which pin of the port. The HCF and HCFD are set by hardware and clear by software. The
HCF should be clear every time by the CLR EVF,#I or MOV HEF,#I instructions before enter the hold
mode. When EVF,EVFD and HEF,HEFD have been reset, the corresponding bit of HCF,HCFD is reset
simultaneously.For more details, refer to the following flow chart.