![](http://datasheet.mmic.net.cn/230000/W742E811_datasheet_15631148/W742E811_62.png)
Preliminary W742C(E)811
- 62 -
Instruction set, continued
Machine code
Flag & Register
Mnemonic
Function
Flag affected
W/C
0101 1101 0xxx xxxx
MOVA
R, EVFL
ACC, R
←
EVF.0 - EVF.3
1/1
0101 1101 1xxx xxxx
MOVA
R, EVFH
ACC, R
←
EVF.4 - EVF.7
1/1
0100 0001 iiii i iii
MOV
HEF, #I
Set/Reset HOLD mode release Enable Flag
1/1
0011 0001 0000 000 i
MOV
HEFD,#I
Set/Reset RD HOLD mode release Enable Flag
1/1
0101 0001 iiii i iii
MOV
IEF, #I
Set/Reset Interrupt Enable Flag
1/1
0100 0011 0000 iiii
MOV
PEF, #I
Set/Reset Port Enable Flag
1/1
0011 0011 0000 ii00
MOV
P1EF, #I
Set/Reset P1 Port Enable Flag
1/1
0101 0010 i iiiiiii
MOV
SEF, #I
Set/Reset STOP mode wake-up Enable Flag for
RC,RD port
1/1
0101 0100 0000 iiii
MOV
SCR, #I
SCR
←
I
1/1
0100 1111 0xxx xxxx
MOVA
R, PSR0
ACC, R
←
Port Status Register 0
ZF
1/1
0100 1111 1xxx xxxx
MOVA
R, PSR1
ACC, R
←
Port Status Register 1
ZF
1/1
0101 1111 0xxx xxxx
MOVA
R, PSR2
ACC, R
←
Port Status Register 2
ZF
1/1
0100 0010 0000 0000
CLR
PSR0
Clear Port Status Register 0
1/1
0100 0010 1000 0000
CLR
PSR1
Clear Port Status Register 1
1/1
0100 0010 1100 0000
CLR
PSR2
Clear Port Status Register 2
1/1
0101 0000 0100 0000
SET
CF
Set Carry Flag
CF
1/1
0101 0000 0000 0000
CLR
CF
Clear Carry Flag
CF
1/1
0001 0111 0000 0000
CLR
DIVR0
Clear the last 4-bit of the Divider 0
1/1
0101 0101 1000 0000
CLR
DIVR1
Clear the last 4-bit of the Divider 1
1/1
0001 0111 1000 0000
CLR
WDT
Clear WatchDog Timer
1/1
Shift & Rotate
0100 1101 0xxx xxxx
SHRC
R
ACC.n, R.n
←
(R.n+1);
ACC.3, R.3
←
0; CF
←
R.0
ZF, CF
1/1
0100 1101 1xxx xxxx
RRC
R
ACC.n, R.n
←
(R.n+1);
ACC.3, R.3
←
CF; CF
←
R.0
ZF, CF
1/1
0100 1100 0xxx xxxx
SHLC
R
ACC.n, R.n
←
(R.n-1);
ACC.0, R.0
←
0; CF
←
R.3
ZF, CF
1/1
0100 1100 1xxx xxxx
RLC
R
ACC.n, R.n
←
(R.n-1);
ACC.0, R.0
←
CF; CF
←
R.3
ZF, CF
1/1