參數(shù)資料
型號(hào): W742E
廠商: WINBOND ELECTRONICS CORP
元件分類: 4位微控制器
英文描述: 4-BIT SINGLE-CHIP MICROCONTROLLER FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTER
中文描述: 4位單片機(jī)的小型通用紅外遙控器
文件頁(yè)數(shù): 39/66頁(yè)
文件大?。?/td> 303K
代理商: W742E
Preliminary W742C(E)811
Publication Release Date: May 1999
- 39 -
Revision A1
Bit 0 = 0 P0.0 & P0.1 work as normal input/output pin;
Bit 0 = 1 P0.0 & P0.1 work as serial port function.
Bit 1 = 0 P0.0 works as serial clock input pin;
Bit 1 = 1 P0.0 works as serial clock output pin.
Bit 2 = 0 Serial data latched/changed at falling edge of clock;
Bit 2 = 1 Serial data latched/changed at rising edge of clock.
Bit 3 = 0 Serial clock output frequency is fosc/2;
Bit 3 = 1 Serial clock output frequency is fosc/256.
At initial reset, SIC = 0000B.
The serial I/O functions are controlled by the instructions SOP R and SIP R. The two instructions are
described below:
(1) When in the first time the SIP R instruction is executed, the data will be loaded from the serial input
buffer to the ACC and RAM. But this data is not meaningful, it is used to enable serial port. There
are two methods to get the serial data, one is interrupt and the other is polling. When enable the
serial input, the bit 1 of port status register 2 (PSR2) will automatically be set to "1" (BUSYI = 1).
Then the P0.0 pin will send out 8 clocks or accept 8 clcoks from external device and the data from
the P0.1 pin will be loaded to SIB buffer at the rising or falling edge of the P0.0 pin. After the 8
clocks have been sent, BUSYI will be reset to "0" and EVF.5 will be set to "1." At this time, if IEF.5
has been set (IEF.5 = 1), an interrupt is executed then the SIP R instruction can get the correct data
from the serial input buffer(SIB), low nibble of SIB movs to ACC register and the high nibble moves
to RAM; if HEF.5 has been set (HEF.5 = 1), the hold state is terminated. The polling method is to
check the status of PSR2.1 (BUSYI) to know whether the serial input process is completed or not. If
a serial input process is not completed, but the SIP R instruction is executed again, the data will be
lost. The timing is shown in Figure 5-12.
T1
T2
T3
T4
Data latch
BUSYI
EVF5
Ins.
P0.1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
rising latch
falling latch
NOTE: The serial clock frequency is fosc/2
SIP R
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