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參數(shù)資料
| 型號： | W78M32VP110BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | PROM |
| 英文描述： | 8M X 32 FLASH 3.3V PROM, 110 ns, PBGA159 |
| 封裝： | 13 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 50/51頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | W78M32VP110BM |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W78M32VP-XBX
January 2010
Rev. 12
White Electronic Designs Corp. reserves the right to change products or specications without notice.
NOTE
The accelerated program functions must not be used more
than 10 times per sector. If the system asserts VHH on this
input, the device automatically enters the aforementioned
Unlock Bypass mode and uses the higher voltage on the
input to reduce the time required for program operations.
The system can then use the Write Buffer Load command
sequence provided by the Unlock Bypass mode. Note that
if a “Write-to-Buffer-Abort Reset” is required while in Unlock
Bypass mode, the full 3-cycle RESET command sequence
must be used to reset the device. Removing VHH from the
ACC input, upon completion of the embedded program
operation, returns the device to normal operation.
Sectors must be unlocked prior to raising WP#/ACC
to VHH.
The WP#/ACC pin must not be at VHH for operations
other than accelerated programming, or device
damage may result.
It is recommended that WP#/ACC apply VHH after
power-up sequence is completed. In addition, it is
recommended that WP#/ACC apply from VHH to VIH/
VIL before powering down VCC/VIO.
UNLOCK BYPASS
This device features an Unlock Bypass mode to facilitate
shorter programming commands. Once the device enters
the Unlock Bypass mode, only two write cycles are required
to program data, instead of the normal four cycles.
This mode dispenses with the initial two unlock cycles
required in the standard program command sequence,
resulting in faster total programming time. The Command
Denitions shows the requirements for the unlock bypass
command sequences.
During the unlock bypass mode, only the Read, Program,
Write Buffer Programming, Write-to-Buffer-Abort Reset,
and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle
unlock bypass reset command sequence. The rst cycle
must contain the sector address and the data 90h. The
second cycle need only contain the data 00h. The sector
then returns to the read mode.
WRITE OPERATION STATUS
The device provides several bits to determine the status of
a program or erase operation. The following subsections
describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: DATA# POLLING
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of
the final WE# pulse in the command sequence. Note
that the Data# Polling is valid only for the last word being
programmed in the write-buffer-page during Write Buffer
Programming. Reading Data# Polling status on any word
other than the last word to be programmed in the write-
buffer-page returns false status information.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed
to DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to read
valid status information on DQ7. If a program address falls
within a protected sector, Data# polling on DQ7 is active,
then that sector returns to the read mode.
During the Embedded Erase Algorithm, Data# polling
produces a “0” on DQ7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data# Polling produces a “1” on DQ7. The system must
provide an address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data# Polling on DQ7
is active for approximately 100 μs, then the device returns
to the read mode. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads DQ7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, DQ7 may change asynchronously with
DQ6-DQ0 while Output Enable (OE#) is asserted low.
That is, the device may change from providing status
information to valid data on DQ7. Depending on when the
system samples the DQ7 output, it may read the status or
valid data. Even if the device has completed the program or
erase operation and DQ7 has valid data, the data outputs
on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
See the following for more information: Table 18, shows the
outputsforData#PollingonDQ7.FIG:7,showstheData#Polling
algorithm; and FIG: 22, shows the Data# Polling timing diagram.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W78M32VP-110BM | 制造商:White Electronic Designs 功能描述:Flash Module Parallel 256Mbit |
| W78M32V-XBX | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx32 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package |
| W78M64VP110SBM | 制造商:Microsemi Corporation 功能描述:8MX64 FLASH 3.3V PAGE MODE - Bulk |
| W78M64V-XSBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash MCP |
| W78NCSX-23 | 功能描述:低信號繼電器 - PCB 4PDT 3A 24VDC IND RoHS:否 制造商:NEC 觸點形式:2 Form C (DPDT-BM) 觸點電流額定值: 線圈電壓:5 V 最大開關(guān)電流:1 A 線圈電流:1 A 線圈類型:Non-Latching 功耗:140 mW 端接類型:SMT 絕緣: 介入損耗: |
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