參數(shù)資料
型號： W89C840F
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器)
中文描述： 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 3/72頁
文件大?。?/td> 731K
代理商： W89C840F
W89C840F
Publication Release Date:April 1997
Revision A1
- 3 -
The W89C840F is a highly integrated Ethernet LAN controller for both 100BaseT and 10BaseT
Ethernet. It provides a host bus interface complying with the PCI local bus specification revision 2.1, and
the MII interface complying with the IEEE802.3u standard for easily implementing an Ethernet LAN
adapter. The built-in 2K bytes transmit FIFO and 4K bytes receive FIFO, controlled by the on-chip bus
master, are designed for improving network performance and reducing the host bus utilization.
The on-chip DMA controller handles the data transfer between the host memory and the FIFOs.
The data received from network are queued into the receive FIFO and then, directly moved into the host
memory through the PCI bus. On the other hand, the transmitted data are fetched from the host memory
and directly queued into the transmit FIFO. No extra on-board memory is needed for data buffering
during the data transceiving operation.
Many versatile registers, including host bus control registers, direct memory access(DMA)
control registers, media access control registers, and signature identification registers, are implemented
for system configuring. All of these long words accessible registers perform the status report and the
precisely control on the transmit and receive operation. It also provides an extra channel for the on-line
application program to update the on-board expansion ROM device in some specific application
environment.
Features
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Complies with IEEE 802.3, 802.3u, ANSI 8802-3 and Ethernet standards
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Supports PCI bus master mode for DMA operation, fully complying with PCI 2.1 standard
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Early interrupt function available for both transmit and receive
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Both half duplex and full duplex available
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Independent deep receive and transmit FIFO and no onboard memory required
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Flexible data structure for host compatibility and system performance
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Supports 25 to 33 Mhz PCI clock speed
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Supports full MII management function
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Provides EEPROM and flash memory on-board programming function
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Supports both big and little endian byte ordering for descriptor and buffer
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Flexible address filtering modes
-- 64-bit hash-table and one perfect address
-- All multicast and promiscuous
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A boot ROM interface, capable of supporting up to 256KB
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Supports programmable sub-vendor ID with automatic loading into configuration register
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Internal and external loopback mode for diagnostic
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Single 5 volt power supply
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100 pins PQFP package
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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