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參數(shù)資料
| 型號： | W89C840F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 100/10Mbps Ethernet Controller(100/10Mbps以太網(wǎng)控制器) |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 6/72頁 |
| 文件大?。?/td> | 731K |
| 代理商： | W89C840F |
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W89C840F
- 6 -
Pin Function Descriptions
1) PCI Interface
Signal Name
Pin
Type
Pin
Number
Pin Description
PCICLK
I
PCI Clock Input:
The W89C840F supports PCI clock rate ranged from
25Mhz to 33MHz continuously. All PCI signals except
RST# and INTA#, are referenced on the rising edge of
this clock.
RSTB
I
Hardware reset signal:
When asserted(active low), all PCI output of W89C840F
will be in high impedance state, and all open drain
signals will be floated. The configurations inside
W89C840F will be in its initial state. This signal must
be asserted for a period of, at least, 10
PCI clocks to
have a reset on hardware correctly.
AD[31:0]
IO/TS
Multiplexed Address and Data bus:
During the first cycle that FRAME# asserts, they act as
an address bus; on the other cycles, they are switched to
be a data bus.
C_BEB[3:0]
IO/TS
Multiplexed command and byte enables:
These signals are driven by current bus master. During
address phase, it means a bus command; on the other
phase, it presents byte enable of the transaction.
PAR
IO/TS
Parity signal.
This PAR represents even parity across AD[31:0] and
C_BEB[3:0]. It has the same timing as AD[31:0] but
delayed by one clock.
FRAMEB
IO/STS
PCI Cycle Frame:
The current bus master asserts FRAMEB to indicate the
beginning and duration of a bus access. This signal will
keep asserted while the current transaction is ongoing
and will keep deasserted to indicate that the next data
phase is the final data phase.
IRDYB
IO/STS
Initiator Ready:
The IRDYB asserted by the current initiator to indicate
the ability to complete the data transfer at the current
data phase. The initiator asserts IRDYB to indicate the
valid write data, or to indicate it is ready to accept the
read data.
More than or exactly one wait state will be
inserted if IRDYB deasserted during the current
transaction. Data is transferred at the clock rising edge
when both IRDYB and TRDYB are asserted at the same
time.
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