參數(shù)資料
型號: W963B6BBN70E
廠商: WINBOND ELECTRONICS CORP
元件分類: SRAM
英文描述: 512K X 16 PSEUDO STATIC RAM, 65 ns, PBGA48
封裝: 6 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁數(shù): 19/29頁
文件大小: 948K
代理商: W963B6BBN70E
W963B6BBN
Timing Waveforms, continued
Power-up Timing #2
CE2
VDD
VDD min
tC2HL
CE1
tC2LP
0V
tCSP
tCHH
tC2HL
tCHS
Note:
The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level.
CE1 must be brought to High prior to or together with CE2 Low to High transition.
Standby Entry Timing after Read or Write
CE1
OE
WE
Active (Read)
Standby
tCHOX
Active (Write)
Standby
tCHWX
Note:
Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min)
period from either last address transition of A0, A1 and A2, or CE1 Low to High transition.
- 26 -
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