參數(shù)資料
型號(hào): W963B6BBN70E
廠商: WINBOND ELECTRONICS CORP
元件分類: SRAM
英文描述: 512K X 16 PSEUDO STATIC RAM, 65 ns, PBGA48
封裝: 6 X 8 MM, 0.75 MM PITCH, TFBGA-48
文件頁(yè)數(shù): 29/29頁(yè)
文件大?。?/td> 948K
代理商: W963B6BBN70E
W963B6BBN
AC Characteristics
(Under Recommended Operating Conditions unless otherwise noted)
Read Operation
-70
-80
PARAMETER
SYM.
Min.
Max.
Min.
Max.
UNIT
NOTES
Read Cycle Time
tRC
70
-
80
-
nS
Chip Enable Access Time
tCE
-
65
-
75
nS
*1, *3
Output Enable Access Time
tOE
-
40
-
45
nS
*1
Address Access Time
tAA
-
65
-
75
nS
*1
Output Data Hold Time
tOH
5
-
5
-
nS
*1
CE1 Low to Output Low-Z
tCLZ
5
-
5
-
nS
*2
OE
Low to Output Low-Z
tOLZ
0
-
0
-
nS
*2
CE1 High to Output High-Z
tCHZ
-
20
-
25
nS
*2
OE
High to Output High-Z
tOHZ
-
20
-
25
nS
*2
Address Setup Time to CE1 Low
tASC
-5
-
-5
-
nS
*4
tASO
30
-
35
-
nS
*3, *5
Address Setup Time to OE Low
tASO[ABS]
10
-
10
-
nS
*6
LB
/ UB Setup Time to CE1 Low
tBSC
-5
-
-5
-
nS
LB
/ UB Setup Time to OE Low
tBSO
10
-
10
-
nS
Address Invalid Time
tAX
-
5
-
5
nS
Address Hold Time from CE1 Low
tCLAH
70
-
80
-
nS
Address Hold Time from OE Low
tOLAH
40
-
45
-
nS
*9
Address Hold Time from CE1 High
tCHAH
-5
-
-5
-
nS
Address Hold Time from OE High
tOHAH
-5
-
-5
-
nS
LB
/ UB Hold Time from CE1 High
tCHBH
-5
-
-5
-
nS
LB
/ UB Hold Time from OE High
tOHBH
-5
-
-5
-
nS
CE1 Low to OE Low Delay Time
tCLOL
25
1000
30
1000
nS
*3, *5, *7, *8
OE
Low to CE1 High Delay Time
tOLCH
35
-
40
-
nS
*7
CE1 High Pulse Width
tCP
12
-
15
-
nS
tOP
25
1000
30
1000
nS
*5, *7, *8
OE
High Pulse Width
tOP[ABS]
12
-
15
-
nS
*6
Publication Release Date: March 11, 2003
- 9 -
Revision A1
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