參數(shù)資料
型號： W9712G8JB-3
廠商： WINBOND ELECTRONICS CORP
元件分類： DRAM
英文描述： DDR DRAM, PBGA60
封裝： 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60
文件頁數(shù)： 47/86頁
文件大小： 1039K
代理商： W9712G8JB-3
W9712G8JB
Publication Release Date: Oct. 12, 2010
- 51 -
Revision A01
30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
PARAMETER
SYMBOL
DDR2-667
DDR2-800
DDR2-1066
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Clock period jitter
tJIT(per)
-125
125
-100
100
-90
90
pS
Clock period jitter during DLL locking period
tJIT(per,lck)
-100
100
-80
80
-80
80
pS
Cycle to cycle clock period
tJIT(cc)
-250
250
-200
200
-180
180
pS
Cycle to cycle clock period jitter during DLL
locking period
tJIT(cc,lck)
-200
200
-160
160
-160
160
pS
Cumulative error across 2 cycles
tERR(2per)
-175
175
-150
150
-132
132
pS
Cumulative error across 3 cycles
tERR(3per)
-225
225
-175
175
-157
157
pS
Cumulative error across 4 cycles
tERR(4per)
-250
250
-200
200
-175
175
pS
Cumulative error across 5 cycles
tERR(5per)
-250
250
-200
200
-188
188
pS
Cumulative error across n cycles,
n = 6 ... 10, inclusive
tERR(6-10per)
-350
350
-300
300
-250
250
pS
Cumulative error across n cycles,
n = 11 ... 50, inclusive
tERR(11-50per)
-450
450
-450
450
-425
425
pS
Duty cycle jitter
tJIT(duty)
-125
125
-100
100
-75
75
pS
Definitions:
- tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCK(avg) =
∑
=
N
j
tCK
1
/ N
where
N = 200
- tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCH(avg) =
∑
=
N
j
tCH
1
/ (N × tCK(avg))
where
N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tCL(avg) =
∑
=
N
j
tCL
1
/ (N × tCK(avg))
where
N = 200
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W971GG6JB 制造商:WINBOND 制造商全稱:Winbond 功能描述:8M ? 8 BANKS ? 16 BIT DDR2 SDRAM
W971GG6JB-18 制造商:Winbond Electronics Corp 功能描述:1GB DDR2 制造商:Winbond Electronics Corp 功能描述:IC DDR2 SDRAM 1GBIT 1.875NS
W971GG6JB-25 制造商:Winbond Electronics Corp 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA 制造商:Winbond Electronics 功能描述:64MBX16 DDR2 制造商:Winbond 功能描述:DRAM Chip DDR2 SDRAM 1G-Bit 64Mx16 1.8V 84-Pin WBGA
W971GG6JB25I 功能描述:IC DDR2 SDRAM 1GBIT 84WBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:32K (4K x 8) 速度:100kHz，400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 125°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOIC 包裝:帶卷 (TR) 其它名稱:CAV24C32WE-GT3OSTR
W971GG6JB-25I 制造商:Winbond Electronics 功能描述:-40~85 1GB DDR2 FOR INDUSTRY
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