參數(shù)資料
型號(hào): W986432EH-7
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 INCH, TSOP2-86
文件頁數(shù): 9/48頁
文件大小: 1180K
代理商: W986432EH-7
W986432EH / W9864G2EH
Publication Release Date: August 17 ,2005
- 17 -
Revision A09
Notes:
1.Operation exceeds “ABSOLUTE MAXIMUM RATING” may cause permanent damage to the
devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up Sequence
(1) Power up must be performed in the following sequence.
(2) Power must be applied to VCC and VCCQ (simultaneously) while all input signals are held in the
“NOP” state. The CLK signals must be started at the same time.
(3) After power-up a pause of at least 200 μseconds is required. It is required that DQM and CKE
signals then be held ‘high‘ (VCC levels) to ensure that the DQ output is impedance.
(4) All banks must be precharged.
(5) The Mode Register Set command must be asserted to initialize the Mode Register.
(6) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of
the device
6. AC Testing Conditions
PARAMETER
CONDITIONS
Output Reference Level
1.4V
Output Load
See diagram below
Input Signal Levels (VIH/VIL)
2.4V/0.4V
Transition Time (Rise and Fall) of Input Signal
1 nS
Input Reference Level
1.4V
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohms
output
50pF
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