參數(shù)資料
型號: WM9712LEFT
廠商: Wolfson Microelectronics
元件分類: Codec
英文描述: AC97 Audio and Touchpanel CODEC
中文描述: AC97音頻編解碼器和觸摸屏
文件頁數(shù): 56/78頁
文件大?。?/td> 689K
代理商: WM9712LEFT
WM9712L
Production Data
w
PD Rev 4.0 December 2003
56
Table 42 Extended Power Down Register (Additional to AC’97 Rev 2.2)
Note:
*When disabling a PGA, always ensure that it is muted first.
ADDITIONAL POWER MANAGEMENT:
AUXDAC: see “Auxiliary DAC” section. AUXDAC is OFF by default.
Touchpanel Interface: see “Controlling the Touchpanel Digitiser / Power Management”.
The touchpanel digitiser is OFF by default.
SLEEP MODE
Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9712L is in
sleep mode. There is in fact a very large number of different sleep modes, depending on the other
control bits. For example, the low-power standby mode described below is a sleep mode. It is
desirable to use sleep modes whenever possible, as this will save power. The following functions do
not require a clock and can therefore operate in sleep mode:
Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode
Pen-down detection
GPIO and interrupts
Battery alarm / analogue comparators (but not battery measurement)
The WM9712L can awake from sleep mode as a result of
A warm reset on the AC-Link (according to the AC’97 specification)
A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see
“GPIO and Interrupt Control” section)
A virtual GPIO event such as pen-down, battery alarm, etc. (see “GPIO and Interrupt
Control” section)
REGISTER
ADDRESS
24h
Additional
power down
control
BIT
LABEL
DEFAULT
DESCRIPTION
15
14
13
12
11
10
9
8
7
6
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
PD7
PD6
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
Disables Crystal Oscillator
Disables left audio DAC
Disables right audio DAC
Disables left audio ADC
Disables right audio ADC
Disables MICBIAS
Disables left headphone mixer
Disables right headphone mixer
Disables speaker mixer
Disables MONO_OUT buffer (pin 33) and phone
mixer
Disables OUT3 buffer (pin 37)
Disables headphone buffers (HPOUTL/R)
Disables speaker outputs (LOUT2, ROUT2)
Disables Line Input PGA (left and right) *
Disables Phone Input PGA *
Disables Mic Input PGA (left and right) *
5
4
3
2
1
0
PD5
PD4
PD3
PD2
PD1
PD0
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
0 (ON)
Note: When analogue inputs or outputs are disabled, they are internally connected to VREF
through a large resistor (VREF=AVDD/2 except in OFF mode, when VREF itself is disabled). This
maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.
相關(guān)PDF資料
PDF描述
WM9712LEFV AC97 Audio and Touchpanel CODEC
WM9712LSEFL AC97 Audio and Touchpanel CODEC
WM9712LSEFT AC97 Audio and Touchpanel CODEC
WM9712LSEFV AC97 Audio and Touchpanel CODEC
WME128K8-XXX 128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
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