參數(shù)資料
型號: WM9712LEFT
廠商: Wolfson Microelectronics
元件分類: Codec
英文描述: AC97 Audio and Touchpanel CODEC
中文描述: AC97音頻編解碼器和觸摸屏
文件頁數(shù): 66/78頁
文件大小: 689K
代理商: WM9712LEFT
WM9712L
Register 1Ch
controls the.recording gain.
REG
ADDR
15
RMU
14
GRL
Production Data
w
PD Rev 4.0 December 2003
66
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
1 (mute)
0 (standard)
Mutes audio ADC input
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls left ADC recording volume
Enables zero-cross detector
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls right ADC recording volume
13:8
7
6
RECVOLL
ZC
GRR
000000 (0dB)
0 (OFF)
0 (standard)
1Ch
5:0
RECVOLR
000000 (0dB)
Audio ADC,
Record Gain
Register 20h
is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the
WM9712L.
REG
ADDR
13
3DE
0 (OFF)
Enables 3D enhancement
20h
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
Audio DACs, 3D Stereo
Enhancement
Intel’s AC’97 Component
Specification, Revision 2.2, page 55
7
LB
0 (OFF)
Enables loopback (i.e. feed ADC output data
directly into DAC)
Register 22h
controls 3D stereo enhancement for the audio DACs.
REG
ADDR
5
3DLC
4
3DUC
3:0
3DDEPTH
Register 24h
is for power management additional to the AC’97 specification. Note that the actual state of each circuit block
depends on both register 24h AND register 26h.
REG
ADDR
15
PD15
0 *
Disables Crystal Oscillator
14
PD14
0 *
Disables left audio DAC
13
PD13
0 *
Disables right audio DAC
12
PD12
0 *
Disables left audio ADC
11
PD11
0 *
Disables right audio ADC
10
PD10
0 *
Disables MICBIAS
9
PD9
0 *
Disables left headphone mixer
8
PD8
0 *
Disables right headphone mixer
7
PD7
0 *
Disables speaker mixer
6
PD6
0 *
Disables MONO_OUT buffer (pin 33) and phone mixer
5
PD5
0 *
Disables OUT3 buffer (pin 37)
4
PD4
0 *
Disables headphone buffers (HPOUTL/R)
3
PD3
0 *
Disables speaker outputs (LOUT2, ROUT2)
2
PD2
0 *
Disables Line Input PGA (left and right)
1
PD1
0 *
Disables Phone Input PGA
0
PD0
0 *
Disables Mic Input PGA (left and right)
* “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0.
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
0 (low)
0 (high)
0000 (0%)
Selects lower cut-off frequency
Selects upper cut-off frequency
Controls depth of 3D effect
22h
Audio DACs,
3D Stereo
Enhancement
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
24h
Power
Management
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