參數(shù)資料
型號(hào)： X1243S8
廠商： INTERSIL CORP
元件分類： XO, clock
英文描述： Real Time Clock/Calendar/Alarm with EEPROM
中文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝： PLASTIC, SOIC-8
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 90K
代理商： X1243S8
X1243
8
Figure 5. Acknowledge Response From Receiver
SCL from Master
Data Output from
Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
—The 2nd Data Byte of a Register Write Operation
(when only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
Slave Address Byte and the Word Address Bytes. This
gives the master access to any one of the words in the
array or CCR. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status regis-
ter in preceding operations to enable the write opera-
tion. See “Writing to the Clock/Control Registers” on
page 6.) Upon receipt of each address byte, the
X1243 responds with an acknowledge. After receiving
both address bytes the X1243 awaits the eight bits of
data. After receiving the 8 data bits, the X1243 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1243 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 6.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1243 will not initiate an internal
write cycle, and will continue to ACK commands.
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