FN8101.1 April 14, 2006 Write Cycle Timing Power-up Timing Notes: (1) Delays are measured from the time V
參數(shù)資料
型號: X1286V14IT1
廠商: Intersil
文件頁數(shù): 23/25頁
文件大?。?/td> 0K
描述: IC RTC/CAL/CPU SUP EE 14-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 時鐘/日歷
特點: 警報器,閏年,監(jiān)控器,監(jiān)視計時器
時間格式: HH:MM:SS:hh(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
7
FN8101.1
April 14, 2006
Write Cycle Timing
Power-up Timing
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
VCC slew rate should be between 0.2mV/sec and 50mV/sec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Note:
(1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
tPUR(1)
Time from Power-up to Read
1
ms
tPUW(1)
Time from Power-uppower-up to Write
5
ms
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(1)
Write Cycle Time
5
10
ms
SCL
SDA
tWC
8th Bit of Last Byte
ACK
Stop
Condition
Start
Condition
X1286
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