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參數(shù)資料
| 型號： | X28C513JIZ-15 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5V, Byte Alterable EEPROM |
| 中文描述： | 64K X 8 EEPROM 5V, 150 ns, PQCC32 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-016AE, LCC-32 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 473K |
| 代理商： | X28C513JIZ-15 |
7
FN8106.2
June 7, 2006
The Toggle Bit I/O
6
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28C512, X28C513 memories that
are frequently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applications.
The timing diagram in Figure 3A illustrates the sequence of
events on the bus. The software flow diagram in Figure 3B
illustrates a method for polling the Toggle Bit.
Hardware Data Protection
The X28C512, X28C513 provide three hardware features
that protect nonvolatile data from inadvertent writes.
- Noise Protection—A WE pulse typically less than 10ns
will not initiate a write cycle.
- Default V
CC
Sense—All write functions are inhibited
when V
CC
is 3.6V.
- Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Write cycle timing specifications must be observed
concurrently.
Software Data Protection
The X28C512, X28C513 offer a software controlled data
protection feature. The X28C512, X28C513 are shipped
from Intersil with the software data protection NOT
ENABLED; that is, the device will be in the standard
operating mode. In this mode data should be protected
during power-up/-down operations through the use of
external circuits. The host would then have open read and
write access of the device once V
CC
was stable.
The X28C512, X28C513 can be automatically protected
during power-up and power-down without the need for
external circuits by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation utilizing the software
algorithm. This circuit is nonvolatile and will remain set for
the life of the device unless the reset command is issued.
Once the software protection is enabled, the X28C512,
X28C513 are also protected from inadvertent and accidental
writes in the powered-up state. That is, the software
algorithm must be issued prior to writing additional data to
the device. Note: The data in the three-byte enable
sequence is not written to the memory array.
CE
OE
WE
X28C512, X28C513
Ready
Last
Write
I/O
6
HIGH Z
*
*
V
OH
V
OL
* Beginning and ending state of I/O
6
will vary.
FIGURE 3A. TOGGLE BIT BUS SEQUENCE
Compare
Ok
X28C512
Ready
No
Yes
Compare
Accum with
Addr N
Load Accum
From Addr N
Last Write
FIGURE 3B. TOGGLE BIT SOFTWARE FLOW
X28C512, X28C513
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28C513JM-12 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513JM-15 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:5V, Byte Alterable EEPROM |
| X28C513JM-20 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C513JM-25 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C513JM-90 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
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