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參數(shù)資料
| 型號(hào)： | X28HC64PIZ-90 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt, Byte Alterable EEPROM |
| 中文描述： | 8K X 8 EEPROM 5V, 90 ns, PDIP28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AB, DIP-28 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 265K |
| 代理商： | X28HC64PIZ-90 |
13
FN8109.1
June 7, 2006
ENDURANCE AND DATA RETENTION
POWER-UP TIMING
CAPACITANCE
T
A
= +25°C, f = 1MHz, V
CC
= 5V
A.C. CONDITIONS OF TEST
MODE SELECTION
Note:
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUITS
SYMBOL TABLE
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Max.
Unit
Cycles
Years
Symbol
t
PUR(3)
t
PUW(3)
Parameter
Typ.
(1)
100
5
Unit
μs
ms
Power-up to read operation
Power-up to write operation
Symbol
C
I/O(3)
C
IN(3)
Parameter
Max.
10
6
Unit
pF
pF
Test Conditions
V
I/O
= 0V
V
IN
= 0V
Input/output capacitance
Input capacitance
Input pulse levels
Input rise and fall times
Input and output timing levels
0V to 3V
5ns
1.5V
CE
L
L
H
OE
L
H
X
WE
H
L
X
Mode
Read
Write
Standby and
write inhibit
Write inhibit
Write inhibit
I/O
D
OUT
D
IN
High Z
Power
Active
Active
Standby
X
X
L
X
X
H
—
—
—
—
5V
1.92k
Ω
30pF
Output
1.37k
Ω
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X28HC64
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