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參數(shù)資料
| 型號(hào)： | X28HC64PIZ-90 |
| 廠商： | INTERSIL CORP |
| 元件分類： | DRAM |
| 英文描述： | 5 Volt, Byte Alterable EEPROM |
| 中文描述： | 8K X 8 EEPROM 5V, 90 ns, PDIP28 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-011AB, DIP-28 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 265K |
| 代理商： | X28HC64PIZ-90 |
15
FN8109.1
June 7, 2006
WRITE CYCLE LIMITS
WE Controlled Write Cycle
Notes: (5) t
WC
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
(6) t
WPH
and t
DW
are periodically sampled and not 100% tested.
Symbol
t
WC(5)
t
AS
t
AH
t
CS
t
CH
t
CW
t
OES
t
OEH
t
WP
t
WPH(6)
t
DV(6)
t
DS
t
DH
t
DW(6)
t
BLC
Parameter
Min.
Typ.
(1)
2
Max.
5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
μs
μs
Write cycle time
Address setup time
Address hold time
Write setup time
Write hold time
CE pulse width
OE High setup time
OE High hold time
WE pulse width
WE HIGH recovery
Data valid
Data setup
Data hold
Delay to next write
Byte load cycle
0
50
0
0
50
0
0
50
50
1
50
0
10
0.15
100
Address
t
AS
t
WC
t
AH
t
OES
t
DS
t
DH
t
OEH
CE
WE
OE
Data In
Data Out
HIGH Z
t
CS
t
CH
t
WP
t
DV
Data Valid
X28HC64
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