參數(shù)資料
型號(hào)： X9520B20IA
廠商： Intersil Corporation
英文描述： Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors
中文描述： 三氯酚，葡萄牙，2kbit EEPROM存儲(chǔ)器，雙電壓監(jiān)視器
文件頁(yè)數(shù)： 16/33頁(yè)
文件大?。?/td> 561K
代理商： X9520B20IA
16
FN8206.0
March 8, 2005
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9520. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires
the setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9520, is incorpo-
rated in the form of the Write Protection pin.
WP: Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9520.
The table below (X9520 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
Additional Data Protection Features
In addition to the preceding features, the X9520 also
incorporates the following data protection functionality:
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
VOLTAGE MONITORING FUNCTIONS
V1 / Vcc Monitoring
The X9520 monitors the supply voltage and drives the
V1RO output HIGH (using an external “pull up” resistor)
if V1 / Vcc is lower than V
TRIP1
threshold. The V1RO
output will remain HIGH until V1 / Vcc exceeds V
TRIP1
for a minimum time of t
PURST
. After this time, the
V1RO pin is driven to a LOW state. See Figure 30.
For the Power-on / Low Voltage Reset function of the
X9520, the V1RO output may be driven HIGH down to a
V1 / Vcc of 1V (V
RVALID
). See Figure 30. Another fea-
ture of the X9520, is that the value of t
PURST
may be
selected in software via the CONSTAT register (See
“POR1, POR0: Power-on Reset bits – (Nonvolatile)” on
page 14.).
It is recommended to stop communication to the device
while V1R0 is HIGH. Also, setting the Manual Reset
(MR) pin HIGH overrides the Power-on / Low Voltage cir-
cuitry and forces the V1RO output pin HIGH (See "MR:
Manual Reset").
MR: Manual Reset
The V1RO output can be forced HIGH externally using
the Manual Reset (MR) input. MR is a de-bounced, TTL
compatible input, and so it may be operated by connect-
ing a push-button directly from V1 / Vcc to the MR pin.
V1RO remains HIGH for time t
PURST
after MR has
returned to its LOW state (See Figure 20). An external
“pull down” resistor is required to hold this pin (nor-
mally) LOW.
X9520 Write Permission Status
Block Lock
Bits
MR
V1RO
V1 / Vcc
0 Volts
0 Volts
t
PURST
Figure 20. Manual Reset Response
0 Volts
V
TRIP1
WP
1
1
1
0
0
0
DCP Volatile Write
Permitted
NO
NO
YES
NO
DCP Nonvolatile
Write Permitted
NO
NO
NO
NO
Write to EEPROM
Permitted
NO
NO
NO
Not in locked region
Write to CONSTAT Register
Permitted
BL0
x
1
0
x
BL1
1
x
0
1
Volatile Bits
NO
NO
NO
YES
Nonvolatile
Bits
NO
NO
NO
YES
1
x
NO
NO
Not in locked region
YES
YES
0
0
YES
YES
Yes (All Array)
YES
YES
X9520
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