參數(shù)資料
型號(hào)： X9520B20IA
廠商： Intersil Corporation
英文描述： Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors
中文描述： 三氯酚，葡萄牙，2kbit EEPROM存儲(chǔ)器，雙電壓監(jiān)視器
文件頁數(shù)： 9/33頁
文件大小： 561K
代理商： X9520B20IA
9
FN8206.0
March 8, 2005
It should be noted that all writes to any DCP of the X9520
are random in nature. Therefore, the Data Byte of con-
secutive write operations to any DCP can differ by an
arbitrary number of bits. Also, setting the bits P1 = 1,
P0 = 1 is a reserved sequence, and will result in no
ACKNOWLEDGE after sending an Instruction Byte on
SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal”
R
WX
(x = 0,1,2) at
the “l(fā)owest” tap position, Therefore, the resistance
between
R
WX
and
R
LX
is a minimum (essentially only
the Wiper Resistance,
R
W
).
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9520 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9520.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9520
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
It should be noted that when reading out the data byte
for DCP0 (64 Tap), the upper two most significant bits
are “unknown” bits. For DCP1 (100 Tap), the upper
most significant bit is an “unknown”. For DCP2 (256
Tap) however, all bits of the data byte are relevant (See
Figure 10).
Slave
Address
Instruction
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data Byte
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 10. DCP Read Sequence
“Dummy” write
READ Operation
101 111
0
00 00
W
T
P
1
P
0
101 111
1
WRITE Operation
-
- -
MSB
LSB
DCPx
x = 0
x = 1
x = 2
“-” = DON’T CARE
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
Byte
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 11. EEPROM Byte Write Sequence
Internal
Device
Address
1 0 1 0 0 0 0
0
WRITE Operation
X9520
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