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參數(shù)資料
| 型號： | XA2C128-7VQG100I |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 128MCELL 80 I/O 100VQFP |
| 產(chǎn)品培訓(xùn)模塊： | CoolRunner-II CPLD Starter Kit |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | CoolRunner II |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 7.0ns |
| 電壓電源 - 內(nèi)部： | 1.7 V ~ 1.9 V |
| 邏輯元件/邏輯塊數(shù)目： | 8 |
| 宏單元數(shù)： | 128 |
| 門數(shù)： | 3000 |
| 輸入/輸出數(shù)： | 80 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
| 包裝： | 托盤 |
XA2C128 CoolRunner-II Automotive CPLD
DS554 (v1.2) June 9, 2009
Product Specification
2
R
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 128-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II Automotive 128-macrocell CPLD is I/O
compatible with various JEDEC I/O standards (see
Table 1). This device is also 1.5V I/O compatible with the
use of Schmitt-trigger inputs.
RealDigital Design Technology
Xilinx CoolRunner-II Automotive CPLDs are fabricated on a
0.18 micron process technology which is derived from lead-
ing edge FPGA product development. CoolRunner-II Auto-
motive CPLDs employ RealDigital technology, a design
technique that makes use of CMOS technology in both the
fabrication and design methodology. RealDigital technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high-performance and low power oper-
ation.
Supported I/O Standards
The CoolRunner-II Automotive 128-macrocell device fea-
tures LVCMOS and LVTTL I/O implementations. See
Table 1 for I/O standard voltages. The LVTTL I/O standard is
a general purpose EIA/JEDEC standard for 3.3V applica-
tions that use an LVTTL input buffer and Push-Pull output
buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V
applications.
Table 1: I/O Standards for XA2C128
IOSTANDARD Attribute
Output VCCIO
Input VCCIO
LVTTL
3.3
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
LVCMOS15(1)
1.5
Notes:
1.
LVCMOS15 requires use of Schmitt-trigger inputs.
Figure 1: ICC vs Frequency
Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25°C)(1)
Frequency (MHz)
0
255075
100
150
Typical ICC (mA)
0.019
3.97
7.95
11.92
15.89
23.83
Notes:
1.
16-bit up/down, Resetable binary counter (one counter per function block).
Frequency (MHz)
DS554_01_052109
I CC
(mA)
0
150
100
50
20
0
10
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| XA2C256 | 制造商:XILINX 制造商全稱:XILINX 功能描述:CoolRunner-II Automotive CPLD |
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