Table 18: Output Timing Adjustments f" />
參數(shù)資料
型號: XA3S1200E-4FTG256I
廠商: Xilinx Inc
文件頁數(shù): 10/37頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN3E 1200K 256FTBGA
標準包裝: 90
系列: Spartan®-3E XA
LAB/CLB數(shù): 8672
邏輯元件/單元數(shù): 19512
RAM 位總計: 516096
輸入/輸出數(shù): 190
門數(shù): 1200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
DS635 (v2.0) September 9, 2009
Product Specification
18
R
Table 18: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
-4 Speed
Grade
Single-Ended Standards
LVTTL
Slow
2 mA
5.41
ns
4 mA
2.41
ns
6 mA
1.90
ns
8 mA
0.67
ns
12 mA
0.70
ns
16 mA
0.43
ns
Fast
2 mA
5.00
ns
4 mA
1.96
ns
6 mA
1.45
ns
8 mA
0.34
ns
12 mA
0.30
ns
16 mA
0.30
ns
LVCMOS33
Slow
2 mA
5.29
ns
4 mA
1.89
ns
6 mA
1.04
ns
8 mA
0.69
ns
12 mA
0.42
ns
16 mA
0.43
ns
Fast
2 mA
4.87
ns
4 mA
1.52
ns
6 mA
0.39
ns
8 mA
0.34
ns
12 mA
0.30
ns
16 mA
0.30
ns
LVCMOS25
Slow
2 mA
4.21
ns
4 mA
2.26
ns
6 mA
1.52
ns
8 mA
1.08
ns
12 mA
0.68
ns
Fast
2 mA
3.67
ns
4 mA
1.72
ns
6 mA
0.46
ns
8 mA
0.21
ns
12 mA
0
ns
LVCMOS18
Slow
2 mA
5.24
ns
4 mA
3.21
ns
6 mA
2.49
ns
8 mA
1.90
ns
Fast
2 mA
4.15
ns
4 mA
2.13
ns
6 mA
1.14
ns
8 mA
0.75
ns
LVCMOS15
Slow
2 mA
4.68
ns
4 mA
3.97
ns
6 mA
3.11
ns
Fast
2 mA
3.38
ns
4 mA
2.70
ns
6 mA
1.53
ns
LVCMOS12
Slow
2 mA
6.63
ns
Fast
2 mA
4.44
ns
HSTL_I_18
0.34
ns
HSTL_III_18
0.55
ns
PCI33_3
0.46
ns
SSTL18_I
0.25
ns
SSTL2_I
–0.20
ns
Differential Standards
LVDS_25
–0.55
ns
BLVDS_25
0.04
ns
MINI_LVDS_25
–0.56
ns
LVPECL_25
Input Only
ns
RSDS_25
–0.48
ns
DIFF_HSTL_I_18
0.42
ns
DIFF_HSTL_III_18
0.55
ns
DIFF_SSTL18_I
0.40
ns
DIFF_SSTL2_I
0.44
ns
Notes:
1.
The numbers in this table are tested using the methodology
presented in Table 19 and are based on the operating conditions
set forth in Table 6, Table 9, and Table 11.
2.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Table 18: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Units
-4 Speed
Grade
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